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W83194AR-WE Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194AR-WE
Beschreibung 200MHZ CLOCK FOR WHITNEY CHIPSET
Hersteller Winbond
Logo Winbond Logo 




Gesamt 16 Seiten
W83194AR-WE Datasheet, Funktion
W83194AR-We
200MHZ CLOCK FOR WHITNEY CHIPSET
1.0 GENERAL DESCRIPTION
The W83194AR-We is a Clock Synthesizer for Intel Whitney chipset. W83194AR-We provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83194AR-We provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI.
The W83194AR-We accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
2 CPU clocks
9 SDRAM clocks for 2 DIMMs
8 PCI synchronous clocks.
Optional single or mixed supply:
(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddA=VddC=2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to 200MHz
I2C 2-Wire serial interface and I2C read back
0.5% and 0.75% center type spread spectrum
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
Two 48 MHz pins for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Nov. 1999
- 1 - Revision 0.50






W83194AR-WE Datasheet, Funktion
W83194AR-We
6.0 SERIAL CONTROL 0REGISTERS
PRELIMINARY
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Frequency Table Setting by I2C (SEL5 ~ SEL0)
SSE SS SS SS SS SS
L5 EL4 EL3 EL2 EL1 EL0
CPU
(MHz)
SDRAM CPU/S
(MHz) DRAM
3V66
(MHz)
PCI(M
Hz)
IOAPIC (MHz)
APIC_SEL=1
IOAPIC (MHz)
APIC_SEL=0
0 0 0 0 0 0 83.3 124.95 2/3 83.30 41.65
00000 1
90
90
1 60.00 30.00
00001 0
75 112.5 2/3 75.00 37.50
0 0 0 0 1 1 72 108 2/3 72.00 36.00
0 0 0 1 0 0 89.07 133.6 2/3 89.07 44.53
0 0 0 1 0 1 95.25 95.25 1 63.50 31.75
0 0 0 1 1 0 121 121
1 80.67 40.33
0 0 0 1 1 1 124 124
1 82.67 41.33
0 0 1 0 0 0 119 119
1 79.33 39.67
0 0 1 0 0 1 114 114
1 76.00 38.00
0 0 1 0 1 0 110 110
1 73.33 36.67
0 0 1 0 1 1 105 105
1 70.00 35.00
0 0 1 1 0 0 66.8 100.2 2/3 66.80 33.40
0 0 1 1 0 1 100.2 100.2 1 66.80 33.40
0 0 1 1 1 0 133.6 133.6 1 66.80 33.40
0 0 1 1 1 1 133.6 100.2 4/3 66.80 33.40
0 1 0 0 0 0 135 101.25 4/3 67.50 33.75
0 1 0 0 0 1 125 125
1 83.33 41.67
0 1 0 0 1 0 127 127
1 84.67 42.33
0 1 0 0 1 1 130 130
1 86.67 43.33
0 1 0 1 0 0 140 140
1 70.00 35.00
0 1 0 1 0 1 136 136
1 68.00 34.00
01011 0
166 166.00 1
83.00 41.50
0 1 0 1 1 1 155 155
1 77.50 38.75
01100 0
150 112.5 4/3 75.00 37.50
0 1 1 0 0 1 117 117
1 78.00 39.00
0 1 1 0 1 0 107 107
1 71.33 35.67
0 1 1 0 1 1 100.9 100.9 1 67.27 33.63
01110 0
145 108.75 4/3 72.50 36.25
0 1 1 1 0 1 140 105 4/3 70.00 35.00
01111 0
138 103.5 4/3 69.00 34.50
01111 1
137 102.75 4/3 68.50 34.25
20.83
15.00
18.75
18.00
22.27
15.88
20.17
20.67
19.83
19.00
18.33
17.50
16.70
16.70
16.70
16.70
16.88
20.83
21.17
21.67
17.50
17.00
20.75
19.38
18.75
19.50
17.83
16.82
18.13
17.50
17.25
17.13
41.65
30.00
37.50
36.00
44.53
31.75
40.33
41.33
39.67
38.00
36.67
35.00
33.40
33.40
33.40
33.40
33.75
41.67
42.33
43.33
35.00
34.00
41.50
38.75
37.50
39.00
35.67
33.63
36.25
35.00
34.50
34.25
Publication Release Date: Nov. 1999
- 6 - Revision 0.50

6 Page









W83194AR-WE pdf, datenblatt
W83194AR-We
7.3 Electronical Characteristics of CPU Clock
Vdd=2.5V +/- 5%; CL=10-20pF
Parameter
Symbol Min Typ
Ouput Impedance
RDSP
13.5
Ouput Impedance
Output Low Voltage
RDSN
VOL
13.5
Output High Voltage
VOH
2.0
Output Low Current
IOL 27
Output High Current
IOH -27
Pull-Up Current Min
IOH(min)
-27
Pull-Up Current Max
IOH(max)
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min)
0.4
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max)
Duty Cycle
Dt 45
Skew
TSK
Jitter
Tsc-c
Max
40
40
0.4
30
-27
-27
1.6
55
175
250
PRELIMINARY
Units
Ohm
Ohm
V
V
MA
MA
MA
MA
ns
Test Conditions
IOL=1mA
IOH=-1mA
Vout = 1.0 V
Vout = 2.0V
10pF Load
ns 20pF Load
% VT=1.25V
ps VT=1.25V
ps VT=1.25V
7.4 Electronical Characteristics of 3V66 Clock
Vdd=3.3V +/- 5%; CL=10-30pF
Parameter
Symbol
Ouput Impedance
Ouput Impedance
RDSP
RDSN
Output Low Voltage
VOL
Output High Voltage
VOH
Output Low Current
IOL
Output High Current
IOH
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min)
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max)
Duty Cycle
Dt
Skew
TSK
Jitter
Tsc-c
Min
15
15
2.4
30
-33
0.4
45
Typ Max Units
Test Conditions
55 Ohm
55 Ohm
0.55
V IOL=1mA
V IOH=-1mA
38 MA
-33 MA
ns 10pF Load
1.6 ns 20pF Load
55 % VT=1.5V
175 ps VT=1.5V
500 ps VT=1.5V
- 12 -
Publication Release Date: Nov. 1999
Revision 0.50

12 Page





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