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Teilenummer | W83178S |
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Beschreibung | 100 MHZ 3-DIMM SDRAM BUFFER | |
Hersteller | Winbond | |
Logo | ||
Gesamt 11 Seiten W83178S
100MHZ 3-DIMM SDRAM BUFFER
W83178S
Data Sheet Revision History
Pages
1 n.a.
2 n.a.
3
4
5
6
7
8
9
10
Dates Version
02/Apr
1.0
Version
On Web
n.a.
1.0
Main Contents
All of the versions before 0.50 are for internal use.
Change version and version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: Sep. 1998
- 1 - Revision 1.0
W83178S
Bytes sequence order for I2C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows[1101 0011] :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
6.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits)
in these two bytes are considered "don't care", they must be sent and will be acknowledge. After
that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
6.2.1 Register 0: (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 11 SDRAM5 (Active / Inactive)
6 1 10 SDRAM4 (Active / Inactive)
5 - - Reserved
4 - - Reserved
3 1 7 SDRAM3 (Active / Inactive)
2 1 6 SDRAM2 (Active / Inactive)
1 1 3 SDRAM1 (Active / Inactive)
0 1 2 SDRAM0 (Active / Inactive)
Publication Release Date: Sep. 1998
- 6 - Revision 1.0
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ W83178S Schematic.PDF ] |
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