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Teilenummer | W78C354 |
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Beschreibung | MONITOR MICROCONTROLLER | |
Hersteller | Winbond | |
Logo | ||
Gesamt 30 Seiten Preliminary W78C354
MONITOR MICROCONTROLLER
GENERAL DESCRIPTION
The W78C354 is a high-performance monitor microcontroller that is based on the embedded 80C32
microcontroller core. The W78C354 includes a 16 KB ROM, 512 byte internal data RAM, a 6-bit A/D
converter, two 12-bit and fourteen 8-bit PWM static DACs, one 12-bit and three 8-bit PWM dynamic
DACs, a sync processor, an I2C port, a DDC port, a watchdog timer, and glue logic specially designed
for monitor applications.
The W78C354 is suitable for monitors applying VESA DDC1/DDC2B/DDC2B+. This product's high
level of integration and the availability of a one-time programmable (OTP) flash PROM version(the
W78E354) help to reduce unit costs, development costs, and development time.
FEATURES
• 80C32 MCU core included
• 20 MHz maximum operating frequency
• 16 KB ROM for program storage
• 512 bytes of on-chip data RAM:
− Lower 256 bytes accessed as in the 80C32
− Higher 256 bytes accessed as an external data memory via "MOVX @Ri".
• One SPI/RS232 port (80C32 standard serial port)
• One external interrupt input
• Two timers/counters
• One 8-bit auto-reload timer for software time base
• PWM DACs:
− Two 12-bit PWM/BRM static DACs
− Fourteen 8-bit PWM static DACs
− One 12-bit PWM/BRM dynamic DAC
− Three 8-bit PWM dynamic DACs
• One 6-bit ADC with 4 multiplexed analog inputs
• Sync processor:
− Horizontal & vertical polarity detector
− Sync separator for composite sync
− Horizontal & vertical frequency counter
− Programmable dummy frequency generator
− Programmable H-clamp pulse output
− Safe operation area (SOA) output
− Self-test pattern output
• One software I2C port
• One DDC port (master/slave mode I2C, supports DDC1/DDC2B/DDC2B+)
• Watchdog timer
• Moire cancellation
• Two 15 mA output pins for driving LED
• Power-low reset
• OTP type: W78E354 (16 KB flash PROM)
• Three package types:
− PLCC68 (W78C/E354P), DIP48 (W78C/E354E), DIP40 (W78C/E354)
Publication Release Date: October 1996
- 1 - Revision A1
W78C354
VDD
Power source
VSS Supervisor
RST
HOUT, VOUT
HIN, VIN
HCLAMP
SOA
TXD
RXD
Reset
Circuit
WDT
Sync.
Processor
Oscillator
Serial
Port
512 x 8
RAM
CPU
CORE
T0 Timer0
T1 Timer1
16K x 8
Mask
ROM
Interrupt
Processor
SDAC
DDAC
ADC
I2C
DDC
Port
I/O
Port
Auto
Reload
Timer
INT0
SDAC0 to 13, BSDAC0 to 1
DDAC0 to 2, BDDAC
ADC0 to 3
VAA, VSSA
ISCL
ISDA
DSCL
DSDA
P2
P4
-6-
6 Page W78C354
BIT NAME
FUNCTION
0 HP Hsync polarity. 0: Positive, 1: Negative.
1 VP Vsync polarity. 0: Positive, 1: Negative.
2
NOH
Set by hardware if no Hsync.
3
NOV
Set by hardware if no Vsync.
2. CONTREG1: Control Register1, Bit-addressable
BIT NAME
FUNCTION
0 ADCS0 ADC channel select bit 0.
1 ADCS1 ADC channel select bit 1.
2 ENDDC1 Enable/Disable DDC1 mode.
0: Disable DDC1 mode; the pin P1.3/DSDA is accessed data in the
DDC2B/2B+ mode.
1: Enable DDC1 mode ; the pin P1.3/DSDA is output data in the DDC1 mode.
3 HCES H-Clamp Edge Select.
0: Pin P1.4 will output H-clamp pluse, if the leading edge of Hsync occurs.
1: Pin P1.4 will output H-clamp pluse, if the trailing edge of Hsync occurs.
4 HCWS0 H-Clamp Width Select bit 0.
5 HCWS1 H-Clamp Width Select bit 1.
6 DUMMYEN Enable/Disable dummy frequency generator.
0: Disable, 1: Enable.
7 ADCSTRT Start ADC conversion.
0: Stop, 1: Start.
3. CONTREG2: Control Register2
BIT NAME
FUNCTION
0
ENVS
Enable/Disable Vsync Separator.
0: Disable, 1: Enable.
1
HSPS
Hout Sync Polarity Select.
0: Positive, 1: Negative.
2
VSPS
Vout Sync Polarity Select.
0: Positive, 1: Negative.
3 - Reserved.
- 12 -
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ W78C354 Schematic.PDF ] |
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