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W40S11-23 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer W40S11-23
Beschreibung Clock Buffer/Driver
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 9 Seiten
W40S11-23 Datasheet, Funktion
W40S11-23
Features
• Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
• Supports three SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel’s latest chip set
• I2C serial configuration interface
• Clock Skew between any two outputs is less than 250 ps
• 1- to 5-ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15,
which is ideal for driving SDRAM DIMMs.
Block Diagram
Clock Buffer/Driver
Key Specifications
Supply Voltages:........................................... VDD = 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................VDD + 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns
Output Edge Rate:.............................................. >1.5 V/ns
Output Clock Skew: .................................................. ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ...............................................15typical
Output Type: ................................................ CMOS rail-to-rail
Pin Configuration
SDATA
SCLOCK
Serial Port
Device Control
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SOIC
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 SDRAM11
26 SDRAM10
25 GND
24 VDD
23 SDRAM9
22 SDRAM8
21 GND
20 VDD
19 SDRAM7
18 SDRAM6
17 GND
16
15
GSCNLDOCK[1]
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 28, 1999 rev. **






W40S11-23 Datasheet, Funktion
Signaling from System Core Logic
Start Condition
SDATA
MSB
11
Slave Address
(First Byte)
0100
LSB
10
MSB
Command Code
(Second Byte)
Byte Count
(Third Byte)
LSB MSB
MSB
Last Data Byte
(Last Byte)
Stop Condition
LSB
SCLOCK
123 45678A12 345678A1234
1234567 8A
SDATA
Signaling by Clock Device
Acknowledgment Bit
from Clock Device
SDATA
SCLOCK
tSTHD
tLOW
tR
tHIGH
tF
tDSU
tDHD
tSP
tSPSU
tSTHD
tSPF
tSPSU

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