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Teilenummer | W40S11-02 |
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Beschreibung | SDRAM Buffer - 2 DIMM (Mobile) | |
Hersteller | Cypress Semiconductor | |
Logo | ||
Gesamt 11 Seiten W40S11-02
SDRAM Buffer - 2 DIMM (Mobile)
Features
• Ten skew-controlled CMOS outputs (SDRAM0:9)
• Supports two SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel®’s latest Mobile chip set
• I2C Serial configuration interface
• Skew between any two outputs is less than 250 ps
• 1 to 5 ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 209-mil
SSOP (Shrink Small Outline Package)
Overview
The Cypress W40S11-02 is a low-voltage, ten-output clock
buffer. Output buffer impedance is approximately 15Ω, which
is ideal for driving SDRAM DIMMs.
Key Specifications
Supply Voltages:........................................... VDD = 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................VDD + 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:9 Propagation Delay: ........1.0 to 5.0 ns
Output Edge Rate:................................................. >1.5 V/ns
Output Skew: ............................................................ ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ........................................15 ohms typical
Output Type: ................................................ CMOS rail-to-rail
Block Diagram
Pin Configuration
SDATA
SCLOCK
Serial Port
Device Control
BUF_IN
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
VDD
SDRAM8
GND
VDD
SDATA [1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 SDRAM7
26 SDRAM6
25 GND
24 VDD
23 SDRAM5
22 SDRAM4
21 GND
20 OE [1]
19 VDD
18 SDRAM9
17 GND
16 GND
15 SCLOCK[1]
Note:
1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE
inputs (should not be relied upon for pulling up to VDD).
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 29, 1999, rev. **
W40S11-02
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a “start bit” as shown in Figure
3. A “stop bit” signifies that a transmission has ended.
As stated previously, the W40S11-02 sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 4.
Sending Data to the W40S11-02
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Figure 3. Serial Data Bus Start and Stop Bit
Stop
Bit
6
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ W40S11-02 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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