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W3100A Schematic ( PDF Datasheet ) - ETC

Teilenummer W3100A
Beschreibung i2Chip W3100A
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
W3100A Datasheet, Funktion
www.i2Chip.com
i2Chip W3100A
Technical Datasheet v1.1
Description
The i2Chip W3100A is an LSI of hardware
protocol stack that provides an easy, low-cost solution
for highD-sepseecdrIinptetrinoent connectivity for digital devices
by allowFienag tsuimrpelse installation of TCP/IP stack in the
hardwaBre.lock Diagram
G
The W3100A offers system designers a quick,
easy way to add Ethernet networking functionality to
any product. Implementing this LSI into a system
can completely offload Internet connectivity and
processing standard protocols from the system,
thereby significantly reducing the software
development cost.
The W3100A contains TCP/IP Protocol Stacks
such as TCP, UDP, IP, ARP and ICMP protocols, as
well as Ethernet protocols such as Data Link Control
and MAC protocol.
The W3100A offers a socket API (Application
Programming Interface) that is similar to the windows
socket API. The chip offers Intel and Motorola
MCU (8051, i386, 6811 tested) bus interface and I2C
for upper-layer and supports standard MII interface for
under-layer Ethernet.
The W3100A can be applied to handheld devices
including Internet phones, VoIP SOC chips, Internet
MP3 players, handheld medical devices, LAN cards
for Web servers, cellular phones and many other non-
portable electronic devices such as large consumer
electronic products.G
Features
G
6/Hardware Internet protocols included:
TCP, IP Ver.4, UDP, ICMP, ARP
6/Hardware Ethernet protocols included:
DLC, MAC
6/Supports 4 independent connections simultaneously
6/Internal ICMP responds to PING commands
6/Protocol processing speed: full-duplex 4~5 Mbps
6/Intel/Motorola MCU bus Interface
6/I2C Interface
6/Standard MII Interface for under-layer physical chip
6/Socket API support for easy application programming
6/Supports full-duplex mode
6/Internal 16Kbytes Dual-port SRAM for data buffer
6/0.35 µm CMOS technology
6/Wide operating voltage:
3.3V internal operation, 5V tolerant 3.3V IOs
6/Small 64 Pin LQFP Package
Block Diagram
MODE0
MODE1
MODE2
/CS
/WR
/RD
/INT
ADDR(14:0)
DATA(7:0)
SCL
SDA
Protocol Engine
ICMP
TCP
IP
DLC
MAC
UDP
ARP
CLOCK
EX T_CL K
RESET
MII Interface
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W3100A Datasheet, Funktion
34 /FDPLX
28, 47, 56
MODE[2–
0]
order to configure the W3100A for Serial MII operation.
I FULL/HALF DUPLEX SELECT: This input pin selects Half/Full
Duplex operation.
This pin must be externally pulled low (typically x k) in order to
configure the W3100A for Full Duplex operation.
0 = Full Duplex
1 = Half Duplex
I MODE SELECT: This input pin selects MCU I/F type and operating
mode of W3100A.
Since each pin is positioned as pull-down internally, clock mode –
the default mode – is selected when the connection is not made.
M2 M1 M0
Description
0 0 0 Clocked Mode where MCU Bus signal is
mode analyzed by W3100A by using the
clock when MCU Bus I/F is in
use.
0 0 1 External Mode where MCU Bus signal is
clocked analyzed by W3100A by using the
mode external clock when MCU Bus I/F
is in use.
0 1 0 Non-
Mode where MCU bus signal is
clocked used directly by W3100A when
mode MCU Bus I/F is in use.
0 1 1 I2C
Mode using I2C for MCU I/F.
mode
1 X X Test
Mode used for testing at the plant.
mode Not to be used by regular users.
Clocked mode, External clocked mode and Non-clocked mode are
used to connect MCU and W3100A when MCU Bus I/F is in use.
Choose an appropriate mode and use it by analyzing the MCU bus
timing. Refer to timing diagram for each mode for more detail.
Table 4: W3100A Power Supply Signal Description
PIN#
Signal I/O
Description
2, 12, 22,
VCC
POSITIVE 3.3V SUPPLY PINS
38, 39, 58
3, 13, 23,
GND
NEGATIVE (GROUND) SUPPLY PINS: a decoupling capacitor is
37, 45, 54,
recommended to be connected between the Vcc and GND pins
57
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W3100A pdf, datenblatt
C1_CR (Channel 1 Command Register) [R/W, 0x01]
This register commands Channel 1 Socket to initialize, connect, close, transmit and receive data.
Sock_Init, Connect, Listen, Close, Send and Recv are used when initializing, establishing a connection,
terminating a connection, sending and receiving data for Channel 1 socket. Each corresponding bit is
automatically cleared after executing the command.
Memory test command is used to verify transmission and reception memory where MCU reads and writes
for the transmission and reception memory. Set memory test bit to ‘1’ to become toggled as ‘0’, ‘1’ and
W3100A acts in memory test mode when in ‘1’. Memory test bit needs to become set at ‘0’ in order for
W3100A to execute normal data transmission and reception.
7
Memory Test
6
Recv
5
Send
4
Close
3
Listen
2
Connect
1
Sock_Init
0
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Symbol
Sock_Init
Connect
Listen
Close
Send
Recv
Memory
Test
Description
Reserved
Sets corresponding protocol at C1_SOPR and opens Channel 1 socket
Command for Channel 1 socket to act in client mode to make a connection
to the server
Command to stand by for connection when Channel 1 socket acts in server
mode
Command to terminate connection and close Channel 1 socket
Command to transmit Channel 1 socket data
Command to receive Channel 1 socket data
Command to set memory test mode
C2_CR, C3_CR (Channel 2, 3 Command Register) [R/W, 0x02, 0x03]
This register commands each Channel 2, 3 sockets to initialize, connect, close, transmit and receive data.
Sock_Init, Connect, Listen, Close, Send and Recv are used when initializing, establishing a connection,
terminating a connection, sending and receiving data for corresponding socket. Each corresponding bit is
automatically cleared after executing the command.
76543210
Recv
Send
Close
Listen
Connect Sock_Init
Bit
D0
Symbol
Reserved
Description
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