Datenblatt-pdf.com


W210 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer W210
Beschreibung Spread Spectrum FTG for VIA K7 Chipset
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 14 Seiten
W210 Datasheet, Funktion
W210
Spread Spectrum FTG for VIA K7 Chipset
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for VIA K7
chipset
• One pair of differential CPU outputs for K7 Processor
• One open-drain CPU output for VIA K7 chipset
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• I2C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
PWRDWN#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
PLL2
÷2
SDRAMIN
I2C is a trademark of Philips Corporation.
CPUT_CS
CPUT0
CPUC0
VDDQ3
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS2
24_48MHz/FS3
VDDQ3
SDRAM0:12
13
Table 1. Mode Input Table
Mode
0
1
Pin 2
CPU_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
CPU
(MHz)
1111
133.3
1110
75
1101
100.2
1100
66.8
1011
79
1010
110
1001
115
1000
120
0111
133.3
0110
83.3
0101
100.2
0100
66.8
0011
124
0010
129
0001
138
0000
143
PCI0:5
(MHz)
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
Spread
Spectrum
±0.5%
±0.5%
±0.5%
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Pin Configuration[1]
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS0*
47 GND
46 CPUT_CS
45 GND
44 CPUC0
43 CPUT0
42 VDDQ3
41 PWRDWN#*
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS2*
25 24_48MHz/FS3^
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 11, 2000, rev. *C






W210 Datasheet, Funktion
W210
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the reservedbits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 07.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 5. Data Bytes 07 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Control Function
Data Byte 0
7 --
-- (Reserved)
6 --
-- SEL_2
5 --
-- SEL_1
4 --
-- SEL_0
3 --
-- Hardware/Software Frequency
Select
2 --
-- SEL_4
1 --
-- SEL_3
0 --
-- (Reserved)
Data Byte 1
7 --
-- (Reserved)
6 --
-- (Reserved)
5 --
-- (Reserved)
4 --
-- (Reserved)
3 --
-- (Reserved) Write to 1
2 --
-- (Reserved) Write to 1
1 --
-- (Reserved) Write to 1
0 -- (Reserved) Write to 1
Data Byte 2
7 --
-- (Reserved)
6
7
PCI0
Clock Output Disable
5 --
-- (Reserved)
4
13
PCI5
Clock Output Disable
3
12
PCI4
Clock Output Disable
2
11
PCI3
Clock Output Disable
1
10
PCI2
Clock Output Disable
0
8
PCI1
Clock Output Disable
Data Byte 3
7 --
-- (Reserved)
6 -- SEL_48MHz SEL_48MHz as the output fre-
quency for 24_48MHz
5 26 48MHz Clock Output Disable
4 25 24_48MHz Clock Output Disable
3 --
-- (Reserved)
2 21, 20, SDRAM8:11 Clock Output Disable
18, 17
Bit Control
01
-- --
See Table 6
See Table 6
See Table 6
Hardware
Software
See Table 6
See Table 6
Normal
Three-stated
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
Low Active
-- --
Low Active
Low Active
Low Active
Low Active
Low Active
--
24 MHz
Low
Low
--
Low
--
48 MHz
Active
Active
--
Active
Default
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
6

6 Page









W210 pdf, datenblatt
W210
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 24 MHz
(24.004 24)/24
m/n PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
tR Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD Duty Cycle
Measured on rising and falling edge at 1.5V
fST Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
24.004
+167
57/34
40
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
CPUCLK_T
Cl
ip p
Clock Chip
CPU
Driver
CPUCLK_C
R8
47
R9
47
Z0 = 52
Length = 5
T1
Z0 = 52
Length = 5
T4
1.5V
Z0 = 52
Length = 3
T2
R1
68
20p
1.5V
Z0 = 52
Length = 3
T5
R3
68
20p
Ordering Information
Ordering Code
Package
Name
W210
H
Document #: 38-00846-C
Figure 5. K7 Open Drain Clock Driver Test Circuit
Package Type
48-pin SSOP (300 mils)
12

12 Page





SeitenGesamt 14 Seiten
PDF Download[ W210 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
W210Spread Spectrum FTG for VIA K7 ChipsetCypress Semiconductor
Cypress Semiconductor
W210TSHIGH VOLTAGE PHOTO MOS RELAYETC
ETC
W2115MC500Rectifier DiodeIXYS
IXYS
W2115MC520Rectifier DiodeIXYS
IXYS
W2115MC600Rectifier DiodeIXYS
IXYS

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche