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W147 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer W147
Beschreibung Frequency Generator for Integrated Core Logic
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 12 Seiten
W147 Datasheet, Funktion
PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• Two copies of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Two copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power-down control
• I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
SEL1
SEL0
00
01
10
11
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
X1
X2
SDATA
SCLK
SEL0:1
XTAL
OSC
PLL REF FREQ
I2C
Logic
D i vi d e r,
D el a y,
and
Phase
Control
Logic
PLL 1
PWRDWN#
VDDQ3
REF/APICDIV
VDDQ2
CPU0:1
2
CPU2_ITP
APIC0:1
2
VDDQ3
3V66_0:1
2
PCI0_ICH
PCI1:7
7
DCLK
SDRAM0:7
8
PLL2
VDDQ3
USB
DOT
Pin Configuration
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GND
55 APIC0
54 APIC1
53 VDDQ2
52 CPU0
51 VDDQ2
50 CPU1
49 CPU2_ITP
48 GND
47 GND
46 SDRAM0
45 SDRAM1
44 VDDQ3
43 SDRAM2
42 SDRAM3
41 GND
40 SDRAM4
39 SDRAM5
38 VDDQ3
37 SDRAM6
36 SDRAM7
35 GND
34 DCLK
33 VDDQ3
32 PWRDWN#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **






W147 Datasheet, Funktion
PRELIMINARY
W147G
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 5.
As shown in Figure 5, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discussed in Spread Spectrum
Clock Generation for the Reduction of Radiated Emissionsby
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5% of the selected fre-
quency. Figure 6 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate value for bit 3 in data byte 0 of the I2C
data stream. Refer to page 8 for more details.
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
MAX.
Figure 5. Typical Clock and SSFTG Comparison
MIN.
Figure 6. Typical Modulation Profile
6

6 Page









W147 pdf, datenblatt
Package Diagram
PRELIMINARY
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
W147G
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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