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W130 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer W130
Beschreibung Spread Spectrum Desktop/Notebook System Clock
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 8 Seiten
W130 Datasheet, Funktion
PRELIMINARY
W130
Spread Spectrum Desktop/Notebook System Clock
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Six copies of CPU Clock
• Eight copies of PCI Clock (synchronous w/CPU clock)
• Two copies of 14.318-MHz IOAPIC Clock
• Two copies of 48-MHz USB Clock
• Three buffered copies of 14.318-MHz reference input
• Input is a 14.318-MHz XTAL or reference signal
• Selectable 100-MHz or 66-MHz CPU Clocks
• Power management control input pins
• Test mode and output three-state capability
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Clock Jitter: ........................................................ 200 ps
CPU0:5 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps
CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-kpull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66# SEL1 SEL0 CPU PCI SPREAD#=0
0 0 0 HI-Z HI-Z Don’t Care
0 0 1 66.6 33.3 ±0.9% Center
0 1 0 66.6 33.3 –1% Down
0 1 1 66.6 33.3 –0.5% Down
1 0 0 X1/2 X1/6 Don’t Care
1 0 1 100 33.3 ±0.9% Center
1 1 0 100 33.3 –1% Down
1 1 1 100 33.3 –0.5% Down
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
CPU_STOP#
100/66#_SEL
SEL0
SEL1
SPREAD#
PCI_STOP#
Stop
Clock
Control
PLL 1
÷2/÷3
Stop
Clock
Control
PWR_DWN#
PPowerr
DDoowwnn
CCoonnttrrooll
PLL2
VDDQ3
REF0
REF1
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
CPU4
CPU5
VDDQ3
PCI_F
PCI1
PCI2
PCI3
VDDQ3
PCI4
PCI5
PCI6
PCI7
VDDQ3
48MHz
48MHz
Pin Configuration
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ3
47 REF2
46 VDDQ2
45 APIC0
44 APIC1
43 VDDQ2
42 CPU0
41 CPU1
40 CPU2
39 CPU3
38 GND
37 VDDQ2
36 CPU4
35 CPU5
34 GND
33 VDDQ3
32 GND
31 PCI_STOP#
30 CPU_STOP#
29 PWRDWN#
28 SPREAD#
27 SEL0
26 SEL1
25 SEL100/66#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **






W130 Datasheet, Funktion
PRELIMINARY
W130
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
Description
tP Period
tH High Time
tL Low Time
tR Output Rise Edge Rate
tF Output Fall Edge Rate
tD Duty Cycle
tJC Jitter, Cycle-to-Cycle
tSK Output Skew
tO CPU to PCI Clock Skew
fST Frequency Stabilization
from Power-up (cold
start)
Zo AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
30
12
12
14
14
45 55
250
500
1.5 4
3
30
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f Frequency, Actual
tR Output Rise Edge Rate
tF Output Fall Edge Rate
tD Duty Cycle
fST Frequency Stabilization
from Power-up (cold start)
Zo AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100MHz
Min. Typ. Max.
14.31818
14
14
45 55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
tD Duty Cycle
Measured on rising and falling edge at 1.5V
45
fST Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
2
2
55
3
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
40
Unit
MHz
V/ns
V/ns
%
ms
6

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