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UPA103G Schematic ( PDF Datasheet ) - NEC

Teilenummer UPA103G
Beschreibung HIGH FREQUENCY NPN TRANSISTOR ARRAY
Hersteller NEC
Logo NEC Logo 




Gesamt 8 Seiten
UPA103G Datasheet, Funktion
DATA SHEET
COMPOUND TRANSISTOR
µPA103
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
FIVE MONOLITHIC 9 GHz fT TRANSISTORS:
Two of these use a common emitter pin and can be used as differential amplifiers
OUTSTANDING hFE LINEARITY
TWO PACKAGE OPTIONS:
µPA103B: Superior thermal dissipation due to studded ceramic package
µPA103G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting
DESCRIPTION AND APPLICATIONS
The µPA103 is a user configurable Silicon bipolar transistor array consisting of a common emitter pair and three
individual bipolar transistors. It is available in a surface mount 14-pin plastic SOP package and a 14-pin ceramic package.
Typical applications include: differential amplifiers and oscillators, high speed comparators, advanced cellular phone
systems, electro-optic and other signal processing up to 1.5 gigabits/second.
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA103B-E1
14-pin ceramic package
µPA103G-E1
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
SYMBOLS
PARAMETERS
UNITS RATINGS
VCBO*
Collector to Base Voltage V
15
VCEO*
Collector to Emitter Voltage
V
6
VEBO*
Emitter to Base Voltage
V
2.5
IC* Collector Current
mA 40
PT Power Dissipation
µPA103B mW
µPA103G mW
650
350
TJ Junction Temperature
µPA103B °C
µPA103G °C
200
125
TSTG
Storage Temperature
µPA103B °C –55 to +200
µPA103G °C –55 to +125
* Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10708EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1995, 1999






UPA103G Datasheet, Funktion
µPA103
NOTES ON CORRECT USE
(1) Observe precautions for handling because of electro-static sensitive devices.
(2) Form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired operation).
(3) Design circuits connected Sub pin to the lowest voltage to prevent latch-up.
(4) Design circuits as each pin voltage difference within 15 V maximum.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered in the following recommended conditions. Other soldering methods and conditions
than the recommended conditions are to be consulted with our sales representatives.
µPA103G
Soldering process
Infrared ray reflow
VPS
Wave soldering
Pin part heating
Soldering conditions
Package peak temperature: 235 °C, Hour: within 30 s. (more than 210 °C),
Time: 2 times, Limited days: no.Note
Package peak temperature: 215 °C, Hour: within 40 s. (more than 200 °C),
Time: 2 times, Limited days: no.Note
Soldering tub temperature: less than 260 °C, Hour: within 10 s.
Time: 1 time, Limited days: no.Note
Pin area temperature: less than 300 °C, Hour: within 3 s./pin
Limited days: no.Note
Recommended
condition symbol
IR35-00-2
VP15-00-2
WS60-00-1
µPA103B
Soldering process
Infrared ray reflow
Partial heating method
Soldering conditions
Peak package’s surface temperature: 230 °C or below,
Reflow time: 10 seconds or below (210 °C or higher),
Number of reflow process: 1, Exposure limit*: None
Terminal temperature: 260 °C or below,
Flow time: 10 seconds or below,
Exposure limit*: None
Symbol
Note It is the storage days after opening a dry pack, the storage conditions are 25 °C, less than 65 % RH.
Caution The combined use of soldering method is to be avoided (However, except the pin area heating
method).
For details of recommended soldering conditions for surface mounting, refer to information
document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
6 Data Sheet P10708EJ2V0DS00

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