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PDF PCA9517 Data sheet ( Hoja de datos )
| Número de pieza | PCA9517 | |
| Descripción | Level translating I2C-bus repeater | |
| Fabricantes | NXP Semiconductors | |
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PCA9517
Level translating I2C-bus repeater
Rev. 03 — 30 January 2007
Product data sheet
1. General description
The PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.
While retaining all the operating modes and features of the I2C-bus system during the
level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage
with only time of flight delays to consider.
The PCA9517 drivers are not enabled unless VCCA is above 0.8 V and VCC is above 2.5 V.
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3VCCA to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
2. Features
I 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
I Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
I Footprint and functional replacement for PCA9515/15A
I I2C-bus and SMBus compatible
1 page  
NXP Semiconductors
PCA9517
Level translating I2C-bus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
PCA9517_3
Product data sheet
3.3 V
1.2 V
10 kΩ
SDA
SCL
BUS
MASTER
400 kHz
10 kΩ
VCCB
SDAB
SCLB
10 kΩ
VCCA
SDAA
SCLA
PCA9517
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
bus B
bus A
002aac201
Fig 4. Typical application
The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When the A-side of the PCA9517 is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3VCCA and causes the internal driver on the
B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the
PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus master in Figure 4 were to write to the slave through the PCA9517, waveforms shown
in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.
On the B bus side of the PCA9517, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517 for a short delay while the A bus side rises above 0.3VCCA then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be
recognized by the PCA9517 and then transmitted to the A bus side.
Multiple PCA9517 A-sides can be connected in a star configuration (Figure 5), allowing all
nodes to communicate with each other.
Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is
connected to the B-side. I2C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
Rev. 03 — 30 January 2007
© NXP B.V. 2007. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
10.1 AC waveforms
input
output
1.5 V
tPHL
80 %
0.6 V
20 %
tt(HL)
1.5 V
tPLH
3.0 V
0.1 V
0.6 V
20 %
80 %
1.2 V
tt(LH)
VOL
002aac207
Fig 10. Propagation delay and transition times;
B-side to A-side
PCA9517
Level translating I2C-bus repeater
input
0.3VCCA
0.3VCCA
VCCA
output
tPHL
80 %
1.5 V
20 %
tt(HL)
tPLH
1.5 V
20 %
80 %
3.0 V
tt(LH)
002aac208
Fig 11. Propagation delay and transition times;
A-side to B-side
input
SDAB, SCLB
0.5 V
Fig 12. Propagation delay
output
SCLA, SDAA
tPLH
50 % if VCCA is less than 2 V
1.5 V if VCCA is greater than 2 V
002aac209
11. Test information
VCC(B)
VCC(A)VCC(B)
RL
PULSE
GENERATOR
VI
DUT
VO
RT CL
002aab649
RL = load resistor; 1.35 kΩ on B-side; 167 Ω on A-side (0.9 V to 2.7 V) and 450 Ω on A-side
(3.0 V to 5.5 V).
CL = load capacitance includes jig and probe capacitance; 57 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 13. Test circuit for open-drain outputs
PCA9517_3
Product data sheet
Rev. 03 — 30 January 2007
© NXP B.V. 2007. All rights reserved.
11 of 19
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