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Teilenummer | A500K130 |
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Beschreibung | ProASIC 500K Family | |
Hersteller | Actel Corp | |
Logo | ||
Gesamt 70 Seiten v3.0
ProASIC™ 500K Family
Features and Benefits
High Capacity
• 100,000 to 475,000 System Gates
• 14k to 63k Bits of Two-Port SRAM
• 106 to 440 User I/Os
Performance
• 33 MHz PCI 32-bit PCI
• Internal System Performance up to 250 MHz
• External System Performance up to 100 MHz
Low Power
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient Logic Cells
High Performance Routing Hierarchy
• Ultra Fast Local Network
• Efficient Long Line Network
• High Speed Very Long Line Network
• High Performance Global Network
Nonvolatile and Reprogrammable Flash
Technology
• Live at Power Up
• No Configuration Device Required
• Retains Programmed Design During Power-Down/
Power-Up Cycles
I/O
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• 3.3V, PCI Compliance (PCI Revision 2.2)
Secure Programming
The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
Standard FPGA and ASIC Design Flow
• Flexibility with Choice of Industry-Standard Front-End
Tools
• Efficient Design Through Front-End Timing and Gate
Optimization
ISP Support
• In-System Programming (ISP) with Silicon Sculptor and
Flash Pro
SRAMs and FIFOs
• Up to 150 MHz Synchronous and Asynchronous Operation
• Netlist Generator Ensures Optimal Usage of Embedded
Memory Blocks
Boundary Scan Test
IEEE Std. 1149.1 (JTAG) Compliant
ProASIC Product Profile
Device
Maximum System Gates
Typical Gates
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
Global Routing Resources
Maximum User I/Os
JTAG
PCI
Package (by Pin Count)
PQFP
PBGA
FBGA
A500K050
100,000
43,000
5,376
14k
6
5,376
4
204
Yes
Yes
208
272
144
A500K130
290,000
105,000
12,800
45k
20
12,800
4
306
Yes
Yes
208
272, 456
144, 256
A500K180
370,000
150,000
18,432
54k
24
18,432
4
362
Yes
Yes
208
456
256
A500K270
475,000
215,000
26,880
63k
28
26,880
4
440
Yes
Yes
208
456
256, 676
February 2002
© 2002 Actel Corporation
1
ProASIC™ 500K Family
LL
Inputs
L
L
LL
L
L
Ultra Fast
Local Lines
(connect a tile to the
adjacent tile, I/O buffer,
or memory block)
L
Figure 4 • Ultra Fast Local Resources
4 Tiles Long
2 Tiles Long
1 Tile Long
LLLLLL
LLLLLL
LLLLLL
LLLLLL
LLLLLL
Logic Tile
1 Tile Long
2 Tiles Long
4 Tiles Long
Logic Cell
Figure 5 • Efficient Long Line Resources
6 v3.0
6 Page ProASIC™ 500K Family
Figure 15 on page 14 gives an example of optimal memory
usage. Ten blocks with 23,040 bits have been used to
generate three memories of various widths and depths.
Figure 16 on page 14 shows how memory can be doubled up
to create extra read ports. In this example, 10 out of 28
blocks of the A500K270 yield an effective 6,912 bits of
multiple port memories. The ACTgen™ software facilitates
building wider and deeper memories for optimal memory
usage.
Table 3 • Basic Memory Configurations
Type
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Write Access
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Read Access
Asynchronous
Asynchronous
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Parity
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Library Cell Name
RAM256x9AA
RAM256x9AAP
RAM256xAST
RAM256xASTP
RAM256x9ASR
RAM256x9ASRP
RAM256x9SA
RAM256xSAP
RAM256x9SST
RAM256x9SSTP
RAM256x9SSR
RAM256x9SSRP
FIFO256xAA
FIFO256x9AAP
FIFO256xAST
FIFO256x9ASTP
FIFO256x9ASR
FIFO256x9ASRP
FIFO256x9SA
FIFO256xSAP
FIFO256x9SST
FIFO256x9SSTP
FIFO256x9SSR
FIFO256x9SSRP
12 v3.0
12 Page | ||
Seiten | Gesamt 70 Seiten | |
PDF Download | [ A500K130 Schematic.PDF ] |
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