QL4016-0PLM Datasheet PDF - ETC
| Part Number | QL4016-0PLM | |
| Description | 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM | |
| Manufacturers | ETC | |
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There is a preview and QL4016-0PLM download ( pdf file ) link at the bottom of this page. Total 18 Pages | ||
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QL4016 QuickRAM Data Sheet
• • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
• 16,000 Usable PLD Gates with 118 I/Os
• 300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
• 10 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
• 5 ns access times, each port independently
accessible
• Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
10
RAM
Blocks
320
High Speed
Logic Cells
Interface
Figure 1: QuickRAM Block Diagram
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL4016 QuickRAM Data Sheet Rev I
[8:0]
[17:0]
[1:0]
WA RE
WD
WE
WCL K
MOD E
RCLK
[8:0]
RA
[17:0]
RD
ASYNCRD
Figure 4: QuickRAM Module
Symbol
tSWA
tHWA
tSWD
tHWD
tSWE
tHWE
tWCRD
Table 2: RAM Cell Synchronous Write Timing
Parameter
Propagation Delays (ns)
Fanout
12345
WA Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WA Hold Time to WCLK
0.0 0.0 0.0 0.0 0.0
WD Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WD Hold Time to WCLK
0.0 0.0 0.0 0.0 0.0
WE Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WE Hold Time to WCLK
0.0 0.0 0.0 0.0 0.0
WCLK to RD (WA=RA)a
5.0 5.3 5.6 5.9 7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
Logic Cells
tSRA
tHRA
tSRE
tHRE
tRCRD
Table 3: RAM Cell Synchronous Read Timing
Parameter
Propagation Delays (ns)
Fanout
12345
RA Setup Time to RCLK
1.0 1.0 1.0 1.0 1.0
RA Hold Time to RCLK
0.0 0.0 0.0 0.0 0.0
RE Setup Time to RCLK
1.0 1.0 1.0 1.0 1.0
RE Hold Time to RCLK
RCLK to RDa
0.0 0.0 0.0 0.0 0.0
4.0 4.3 4.6 4.9 6.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25 × C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
© 2002 QuickLogic Corporation
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www.quicklogic.com
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for QL4016-0PLM electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ QL4016-0PLM.PDF Datasheet ] | |
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