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Teilenummer | QL4016-0CF100I |
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Beschreibung | 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM | |
Hersteller | ETC | |
Logo | ||
Gesamt 18 Seiten QL4016 QuickRAM Data Sheet
• • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
• 16,000 Usable PLD Gates with 118 I/Os
• 300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
• 10 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
• 5 ns access times, each port independently
accessible
• Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
10
RAM
Blocks
320
High Speed
Logic Cells
Interface
Figure 1: QuickRAM Block Diagram
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL4016 QuickRAM Data Sheet Rev I
Symbol
RPDRD
Table 4: RAM Cell Asynchronous Read Timing
Parameter
Propagation Delays (ns)
Fanout
RA to RDa
12345
3.0 3.3 3.6 3.9 5.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
tIN
tINI
tISU
tIH
tICLK
tIRST
tIESU
tIEH
Table 5: Input-Only / Clock Cells
Parameter
Propagation Delays (ns)
Fanout
1 2 3 4 8 12 24
High Drive Input Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
High Drive Input, Inverting Delay
1.6 1.7 .19 2.0 2.5 3.0 4.5
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
Input Register Reset Delay
0.6 0.7 0.9 1.0 1.5 2.0 3.5
Input Register Clock Enable Setup Time
2.3 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Symbol
tACK
tGCKP
tGCKB
Table 6: Clock Cells
Parameter
Propagation Delays (ns)
Fanouta
1 2 3 4 8 10 11
Array Clock Delay
1.2 1.2 1.3 1.3 1.5 1.6 1.7
Global Clock Pin Delay
0.7 0.7 0.7 0.7 0.7 0.7 0.7
Global Clock Buffer Delay
0.8 0.8 0.9 0.9 1.1 1.2 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The global
clock has up to 11 loads per half column.
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© 2002 QuickLogic Corporation
6 Page QL4016 QuickRAM Data Sheet Rev I
JTAG
TCK
TMS
TRSTB
TAp Controller
State Machine
(16 States)
Instruction Decode
&
Control Logic
RDI Mux
Instruction Register
Boundary-Scan Register
(Data Register)
Mux TDO
Bypass
Register
Internal
Register
I/O Registers
User Defined Data Register
Figure 10: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges. One of these challenges concerns the accessibility of test points. The Joint Test
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard
1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port
(TAP) controller works in concert with the Instruction Register (IR); these allow users to run
three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
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www.quicklogic.com
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© 2002 QuickLogic Corporation
12 Page | ||
Seiten | Gesamt 18 Seiten | |
PDF Download | [ QL4016-0CF100I Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
QL4016-0CF100C | 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM | ETC |
QL4016-0CF100I | 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM | ETC |
QL4016-0CF100M | 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM | ETC |
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