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SM-BF50 Schematic ( PDF Datasheet ) - Mini-Circuits

Teilenummer SM-BF50
Beschreibung 50OHM DC to 2 GHz
Hersteller Mini-Circuits
Logo Mini-Circuits Logo 




Gesamt 26 Seiten
SM-BF50 Datasheet, Funktion
Standard EEPROM ICs
SLx 24C64
64 Kbit (8192 × 8 bit)
Serial CMOS-EEPROM with
I2C Synchronous 2-Wire Bus
Data Sheet Preliminary 1998-07-27






SM-BF50 Datasheet, Funktion
SLx 24C64
2 Description
The SLx 24C64 device is a serial electrically erasable and programmable read only
memory (EEPROM), organized as 8192 × 8 bit. The data memory is divided into
256 pages. The 32 bytes of a page can be programmed simultaneously.
The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select
pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits
operation down to 2.7 V with low active and standby currents. All devices have a
minimum endurance of 106 erase/write cycles.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at
2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V
type (VCC = 4.5 … 5.5 V) with two temperature ranges for industrial and automotive
applications and as 3 V type (VCC = 2.7 … 5.5 V) for industrial applications. The
EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.
V SS V CC
CS0 CS1 CS2 WP
Start/
Stop
Logic
SCL
SDA
Figure 2
Block Diagram
Semiconductor Group
Chip Address
Control
Logic
Serial
Control
Logic
Programming
Control
H.V. Pump
Address
Logic
X
DEC
EEPROM
Page Logic
Y DEC
Dout/ACK
IEB02525
6 Preliminary 1998-07-27

6 Page









SM-BF50 pdf, datenblatt
SLx 24C64
5.2 Page Write
Address Setting
Transmission of Data
Programming Cycle
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address bytes AHI/ALO are
followed by a sequence of one to a maximum of 32 data bytes
with the new data to be programmed. These bytes are
transferred to the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by AHI (A8 to A12) and ALO (A0 to
A7). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A5 through A12.
Only the respective five least significant address bits A0
through A4 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
Writing over the page border will cause the address counter to
roll over to the first address of the page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Those bytes of the page that have not been addressed are not included in the
programming.
S
T Command
Bus Activity A Byte
Master R CSW
T
EEPROM
Address
AHI
EEPROM
Address
ALO
Data
Byte n
Data ... Data
Byte n+1 Byte n+31
S
T
O
P
SDA Line S
0
P
Bus Activity
EEPROM
AAAAAA
CCCCCC
KKKKKK
IED02519
Figure 8
Page Write Sequence
Semiconductor Group
12 Preliminary 1998-07-27

12 Page





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