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PDF SL4520BN Data sheet ( Hoja de datos )
| Número de pieza | SL4520BN | |
| Descripción | Dual Up-Counter | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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SL4520B
Dual Up-Counter
High-Voltage Silicon-Gate CMOS
The SL4520B Dual Binary Up-Counter consists two identical,
internally synchronous 4-stage counters. The counter stages are D-
type flip-flops having interchangeable CLOCK and ENABLE lines for
incrementing on either the positive-going or negative-going transition.
For single-unit operation the ENABLE input is maintained high and the
counter advances on each positive-going transition of the CLOCK. The
counters are cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple mode by connecting Q4
to the enable input of the subsequent counter while the CLOCK input
of the latter is held low.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4520BN Plastic
SL4520BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8= GND
FUNCTION TABLE
Inputs
Outputs
CLOCK ENABLE RESET
Mode
H L Increment Counter
L L Increment Counter
X L No Change
X L No Change
L L No Change
H L No Change
X X H Q1 thru Q4=L
X = don’t care
SLS
System Logic
Semiconductor
1 page  
SL4520B
Figure 3. Switching Waveforms
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
(1/2 of the Device)
SLS
System Logic
Semiconductor
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet SL4520BN.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SL4520B | Dual Up-Counter | System Logic Semiconductor |
| SL4520BD | Dual Up-Counter | System Logic Semiconductor |
| SL4520BN | Dual Up-Counter | System Logic Semiconductor |
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