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SMP08FP Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer SMP08FP
Beschreibung Octal Sample-and-Hold with Multiplexed Input
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
SMP08FP Datasheet, Funktion
a
Octal Sample-and-Hold
with Multiplexed Input
SMP08*
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
FUNCTIONAL BLOCK DIAGRAM
(LSB)
INPUT A
(MSB)
B C INH
3 11 10 9
6
1 OF 8 DECODER
SW
8 DGND
16 VDD
13 CH0OUT
SW 14 CH1OUT
SW 15 CH2OUT
SW 12 CH3OUT
SW 1 CH4OUT
SW 5 CH5OUT
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
± 1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
SW
SW
HOLD CAPS
(INTERNAL)
SMP08
2 CH6OUT
4 CH7OUT
7 VSS
The SMP08 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over dis-
crete designs. It is available in a 16-pin plastic DIP, or surface-
mount SOIC package.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996






SMP08FP Datasheet, Funktion
SMP08
R3
6.5k
R2 R2 R2 R2
10k10k10k10k
R4
1k
VCC
+15V
D1
C1
10µF
+
R1 C2
101µF
1 16
2 15
3 14
SMP08
4 13
5 12
6 11
7 10
89
R2 R2 R2 R2
10k10k10k10k
Figure 17. Burn-In Circuit
APPLICATIONS INFORMATION
The SMP08, a multiplexed octal S/H, minimizes board space in
systems requiring cycled calibration or an array of control volt-
ages. When used in conjunction with a low cost 16-bit D/A, the
SMP08 can easily be integrated into microprocessor based sys-
tems. Since the SMP08 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP08 has an internally regulated TTL supply so that TTL/
CMOS compatibility is maintained over the full supply range.
See Figure 18 for channel decode address information.
POWER SUPPLIES
The SMP08 is capable of operating with either single or dual
supplies, over a voltage range of 7 volts to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the input and
output voltage range, which is:
(VSS +0.06 V) VOUT/IN (VDD –2 V)
Note that several specifications, including acquisition time, off-
set and output voltage compliance, will degrade for supply volt-
ages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin and any
noise will appear at the outputs.
In single supply applications, it is extremely important that the
VSS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise perfor-
mance. The analog and digital ground traces on the circuit
board should be physically separated to reduce digital switching
noise from entering the analog circuitry.
POWER SUPPLY SEQUENCING
VDD should be applied to the SMP08 before the logic input sig-
nals. The SMP08 has been designed to be immune to latchup,
but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. The hold step (magni-
tude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset), is about 2.5 mV with little variation
over the full output voltage range, TA = +25°C to +85°C. The
droop rate of a held channel is 2 mV/s typical and 20 mV/s
maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA, over the full voltage
range, but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be ob-
tained by restricting the output range to 2 V from either supply.
On-chip SMP08 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with ca-
pacitive loads up to 500 pF. However, since the SMP08’s
buffer outputs are not short-circuit protected, care should be
taken to avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)
The signal input should be driven from a low impedance volt-
age source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the
SMP08’s acquisition time characteristics are to be maintained.
As with all CMOS devices, all input voltages should be kept
within range of the supply rails (VSS < VIN < VDD) to avoid the
possibility of latchup. If single supply operation is desired, op
amps such as the OP183 or AD820 that have input and output
voltage compliances including ground, can be used to drive the
inputs. Split supplies, such as ± 7.5 V, can be used with the
SMP08.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and unused analog inputs connected to analog ground. For
connector-driven analog inputs that may become temporarily
disconnected, a resistor to VDD, VSS or analog ground should
be used with a value ranging from 200 kto 1 M.
–6– REV. D

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