Datenblatt-pdf.com


TE28F020-120 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer TE28F020-120
Beschreibung 28F020 2048K (256K X 8) CMOS FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
TE28F020-120 Datasheet, Funktion
E
28F020 2048K (256K X 8) CMOS
FLASH MEMORY
n Flash Electrical Chip-Erase
2 Second Typical Chip-Erase
n Quick-Pulse Programming Algorithm
10 µS Typical Byte-Program
4 second Chip-Program
n 100,000 Erase/Program Cycles
n 12.0 V ±5% VPP
n High-Performance Read
90 ns Maximum Access Time
n CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n Integrated Program/Erase Stop Timer
n Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n Noise Immunity Features
±10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
n ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n Extended Temperature Options
Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after sale. The 28F020 increases
memory flexibility, while contributing to time and cost savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of eight bits. Intel’s 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to
JEDEC standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F020 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel’s 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates
into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from –1 V to VCC + 1 V.
With Intel’s ETOX process technology base, the 28F020 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290245-009






TE28F020-120 Datasheet, Funktion
E28F020
VVVCSPSPC
WE#
CE#
OE#
State
Control
Command
Register
Integrated Stop
Timer
A0 - A17
Erase Voltage
Switch
To Array Source
DQ0 - DQ7
Input/Output
Buffers
PGM Voltage
Switch
Chip Enable
Output Enable
Logic
STB
Data Latch
STB
Y-Decoder
X-Decoder
Y-Gating
2,097,152 Bit
Cell Matrix
Symbol
A0–A17
DQ0–DQ7
CE#
OE#
WE#
VPP
VCC
VSS
6
Figure 1. 28F020 Block Diagram
0245_01
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
Table 1. Pin Description
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are
internally latched during a write cycle.
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active
high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low; CE# high
deselects the memory device and reduces power consumption to
standby levels.
OUTPUT ENABLE: Gates the devices output through the data
buffers during a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the control register and the
array. Write enable is active low. Addresses are latched on the
falling edge and data is latched on the rising edge of the WE#
pulse.
Note: With VPP 6.5 V, memory contents cannot be altered.
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
DEVICE POWER SUPPLY (5 V ±10%)
GROUND

6 Page









TE28F020-120 pdf, datenblatt
E28F020
The 28F020 contains an intelligent identifier
operation to supplement traditional PROM-
programming methodology. The operation is
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of BDH. To terminate the operation, it
is necessary to write another valid command into
the register.
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the VPP pin.
In the absence of this high voltage, memory
contents are protected against erasure. Refer to
AC Characteristics—Write/Erase/Program Only
Operations and waveforms for specific timing
parameters.
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array
in parallel. After each erase operation, all bytes
must be verified. The erase verify operation is
initiated by writing A0H into the command register.
The address for the byte to be verified must be
supplied as it is latched on the falling edge of the
WE# pulse. The register write terminates the erase
operation with the rising edge of its WE# pulse.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
12
In the case where the data read is not FFH,
another erase operation is performed. (Refer to
Section 2.2.2.3, Set-Up Erase/Erase Commands.)
Verification then resumes from the address of the
last verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this point, the verify
operation is terminated by writing a valid command
(e.g., Program Set-Up) to the command register.
Figure 5, the 28F020 Quick-Erase Algorithm
flowchart, illustrates how commands and bus
operations are combined to perform electrical
erasure of the 28F020. Refer to AC
Characteristics—Write/Erase/Program Only Oper-
ations and waveforms for specific timing
parameters.
2.2.2.5
Set-Up Program/Program
Commands
Set-Up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming operation. The programming
operation terminates with the next rising edge of
WE# used to write the Program Verify command.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and waveforms for specific timing
parameters.
2.2.2.6
Program Verify Command
The 28F020 is programmed on a byte-by-byte
basis. Byte programming may occur sequentially or
at random. Following each programming operation,
the byte just programmed must be verified.
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison

12 Page





SeitenGesamt 30 Seiten
PDF Download[ TE28F020-120 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
TE28F020-12028F020 2048K (256K X 8) CMOS FLASH MEMORYIntel Corporation
Intel Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche