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TE28F010-150 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer TE28F010-150
Beschreibung 28F010 1024K (128K X 8) CMOS FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
TE28F010-150 Datasheet, Funktion
E
28F010 1024K (128K X 8) CMOS
FLASH MEMORY
8
n Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
n Quick-Pulse Programming Algorithm
10 µs Typical Byte-Program
2 Second Chip-Program
n 100,000 Erase/Program Cycles
n 12.0 V ±5% VPP
n High-Performance Read
90 ns Maximum Access Time
n CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n Integrated Program/Erase Stop Timer
n Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n Noise Immunity Features
±10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
n ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of eight bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F010 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on
address and data pins, from –1 V to VCC + 1 V.
With Intel's ETOX process technology base, the 28F010 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290207-012






TE28F010-150 Datasheet, Funktion
E
28F010
290207-1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A0–A16
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0–DQ7
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state off when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders
and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.
Note: With VPP 6.5 V, memory contents cannot be altered.
6

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TE28F010-150 pdf, datenblatt
E
28F010
is necessary to write another valid command into
the register.
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the pin. In the
absence of this high voltage, memory contents are
protected against erasure. Refer to AC
Characteristics—Write/Erase/Program Only Oper-
ations and waveforms for specific timing
parameters.
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The
address for the byte to be verified must be supplied
as it is latched on the falling edge of the WE# pulse.
The register write terminates the erase operation
with the rising edge of its WE# pulse.
The 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer Section
2.2.2.3, Set-Up Erase/Erase Commands.)
Verification then resumes from the address of the
last-verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this
12
point, the verify operation is terminated by writing a
valid command (e.g., Program Set-Up) to the
command register. Figure 5, the 28F010 Quick-
Erase Algorithm flowchart, illustrates how
commands and bus operations are combined to
perform electrical erasure of the 28F010. Refer to
AC Characteristics—Write/Erase/Program Only
Operations and waveforms for specific timing
parameters.
2.2.2.5
Set-Up Program/Program
Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming operation. The programming
operation terminates with the next rising edge of
WE#, used to write the Program Verify command.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and Waveforms for specific timing
parameters.
2.2.2.6
Program Verify Command
The 28F010 is programmed on a byte-by-byte
basis. Byte programming may occur sequentially or
at random. Following each programming operation,
the byte just programmed must be verified.
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming
then proceeds to the next desired byte location.
Figure 5, the 28F010 Quick-Pulse Programming
Algorithm flowchart, illustrates how commands are
combined with bus operations to perform byte

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