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TE28F008BET120 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer TE28F008BET120
Beschreibung 8-MBIT (512K X 16/ 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
TE28F008BET120 Datasheet, Funktion
E
PRODUCT PREVIEW
8-MBIT (512K X 16, 1024K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B
28F800CE-T/B, 28F008BE-T/B
Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Program Time Reduced 60% at
12V VPP
Very High Performance Read
5V: 70/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 120/150 ns Max Access
65 ns Max. Output Enable Time
2.7V: 120 ns Max Access
65 ns Max. Output Enable Time
Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at 2.7–3.6V
x8/x16-Selectable Input/Output Bus
28F800 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F008B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Seven 128-KB Main Blocks
Top or Bottom Boot Locations
Absolute Hardware-Protection for Boot
Block
Software EEPROM Emulation with
Parameter Blocks
Extended Temperature Operation
–40°C to +85°C
Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
Automated Word/Byte Write and Block
Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Erase/Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
Footprint Upgradeable from 2-Mbit and
4-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995
September 1995
Order Number: 290539-002






TE28F008BET120 Datasheet, Funktion
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
E
The Command User Interface (CUI) serves
as the interface between the microprocessor
or microcontroller and the internal
operation of the boot block flash memory
products. The internal Write State Machine
(WSM) automatically executes the
algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the
status of the WSM and whether it
successfully completed the desired program
or erase operation.
Program and erase automation allows
program and erase operations to be
executed using an industry-standard two-
write command sequence to the CUI. Data
writes are performed in word (28F800
family) or byte (28F800 or 28F008B
families) increments. Each byte or word in
the flash memory can be programmed
independently of other memory locations,
unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash
memory family is also designed with an
Automatic Power Savings (APS) feature
which minimizes system battery current
drain, allowing for very low power designs.
To provide even greater power savings, the
boot block family includes a deep power-
down mode which minimizes power
consumption by turning most of the flash
memory’s circuitry off. This mode is
controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides
protection against unwanted command
writes due to invalid system bus conditions
that may occur during system reset and
power-up/down sequences. For example,
6
when the flash memory powers-up, it
automatically defaults to the read array
mode, but during a warm system reset,
where power continues uninterrupted to the
system components, the flash memory
could remain in a non-read mode, such as
erase. Consequently, the system Reset
signal should be tied to RP# to reset the
memory to normal read mode upon
activation of the Reset signal (see Section
3.6).
The 28F800 provides both byte-wide or
word-wide input/output, which is
controlled by the BYTE# pin. Please see
Table 2 and Figure 13 for a detailed
description of BYTE# operations,
especially the usage of the DQ15/A–1 pin.
PRODUCT PREVIEW

6 Page









TE28F008BET120 pdf, datenblatt
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
E
Symbol
WP#
BYTE#
VCC
VPP
GND
12
Table 2. 28F800/008B Pin Descriptions (Continued)
Type
Name and Function
INPUT
WRITE PROTECT: Provides a method for unlocking the
boot block in a system without a 12V supply.
When WP# is at logic low, the boot block is locked ,
preventing program and erase operations to the boot block. If
a program or erase operation is attempted on the boot block
when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to
indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and
can be programmed or erased.
NOTE: This feature is overridden and the boot block
unlocked when RP# is at VHH. This pin is not available on the
44-lead PSOP package. See Section 3.4 for details on write
protection.
INPUT
BYTE# ENABLE: Not available on 28F008B. Controls
whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# pin must be controlled at
CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is
enabled, where data is read and programmed on DQ0–DQ7
and DQ15/A–1 becomes the lowest order address that decodes
between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is
enabled, where data is read and programmed on DQ0–DQ15.
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V,
2.7V–3.6V
PROGRAM/ERASE POWER SUPPLY: For erasing
memory array blocks or programming data in each block, a
voltage either of 5V ± 10% or 12V ± 5% must be applied to
this pin. When VPP < VPPLK all blocks are locked and
protected against Program and Erase commands.
GROUND: For all internal circuitry.
PRODUCT PREVIEW

12 Page





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