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PDF TP3406V Data sheet ( Hoja de datos )
| Número de pieza | TP3406V | |
| Descripción | DASL Digital Adapter for Subscriber Loops | |
| Fabricantes | National Semiconductor | |
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November 1992
TP3406
DASL Digital Adapter for Subscriber Loops
General Description
The TP3406 is a complete monolithic transceiver for data
transmission on twisted pair subscriber loops It is built on
National’s double poly microCMOS process and requires
only a single a5 Volt supply Alternate Mark Inversion (AMI)
line coding in which binary ‘1’s are alternately transmitted
as a positive pulse then a negative pulse is used to ensure
low error rates in the presence of noise with lower emi radia-
tion than other codes such as Bi-phase (Manchester)
Full-duplex transmission at 144 kb s is achieved on a single
twisted wire pair using a burst-mode technique (Time Com-
pression Multiplexed) Thus the device operates as an ISDN
‘U’ Interface for short loop applications typically in a PBX
environment providing transmission for 2 B channels and 1
D channel On 24 cable the range is up to 800 meters
System timing is based on a Master Slave configuration
with the line card end being the Master which controls loop
timing and synchronisation All timing sequences necessary
for loop activation and de-activation are generated on-chip
Selection of Master and Slave mode operation is pro-
grammed via the Microwire Control Interface
A 2 048 MHz clock which may be synchronized to the sys-
tem clock controls all transmission-related timing functions
Block Diagram
Features
Complete ISDN PBX 2-Wire Data Transceiver including
Y 2 B plus D channel interface for PBX U Interface
Y 144 kb s full-duplex on 1 twisted pair using Burst Mode
Y Loop range up to 800 meters ( 24AWG)
Y Alternate Mark Inversion coding with transmit filter and
scrambler for low emi radiation
Y Adaptive line equalizer
Y On-chip timing recovery no external components
Y Standard TDM interface for B channels
Y Separate interface for D channel
Y 2 048 MHz master clock
Y Driver for line transformer
Y 4 loop-back test modes
Y Single a5V supply
Y MICROWIRETM compatible serial control interface
Y Applications in
PBX Line Cards
Terminals
Regenerators
Y Available in 28-pin PLCC Package
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11725
TL H 11725 – 1
RRD-B30M115 Printed in U S A
1 page  
Functional Description (Continued)
BURST MODE OPERATION
For full-duplex operation over a single twisted-pair burst
mode timing is used with the line-card (exchange) end of
the link acting as the timing Master
Each burst from the Master consists of the B1 B2 and D
channel data from 2 consecutive frames combined in the
format shown in Figure 5 During transmit bursts the Mas-
ter’s receiver input is inhibited to avoid disturbing the adap-
tive circuits The Slave’s receiver is enabled at this time and
it synchronizes to the start bit of the burst which is always
an unscrambled ‘1’ (of the opposite polarity to the last ‘1’
sent in the previous burst) When the Slave detects that 36
bits following the start bit have been received it disables the
receiver input waits 6 line symbol periods to match the oth-
er end settling guard time and then begins to transmit its
burst back towards the Master which by this time has en-
abled its receiver input The burst repetition rate is thus
4 kHz which can either free-run or be locked to a synchro-
nizing signal at the Master end by means of the MBS input
(See Figure 10 ) In the latter case with all Master-end
transmitters in a system synchronized together near-end
crosstalk between pairs in the same cable binder may be
eliminated with a consequent increase in signal-to-noise ra-
tio (SNR)
ACTIVATION AND LOOP SYNCHRONIZATION
Activation (i e power-up and loop synchronization) is typi-
cally completed in 50 ms and may be initiated from either
end of the loop If the Master is activating the loop it sends
normal bursts of scrambled ‘1’s which are detected by the
Slave’s line-signal detect circuit causing it to set C0 e 1 in
the Status Register and pull the INT pin low Pin 6 the LSD
pin also pulls low To proceed with Activation the device
must be powered up by writing to the Control Register with
C6 e 1 The Slave then replies with bursts of scrambled
‘1’s synchronized to received bursts and the flywheel circuit
at each end searches for 4 consecutive correctly formatted
receive bursts to acquire full loop synchronization Each re-
ceiver indicates when it is correctly in sync with received
bursts by setting the C1 bit in the Status Register high and
pulling INT low
To activate the loop from the Slave end bit C6 in the Con-
trol Register must be set high which will power-up the de-
vice and begin transmission of alternate bursts i e the burst
repetition rate is 2 kHz not 4 kHz At this point the Slave is
running from its local oscillator and is not receiving any sync
information from the Master When the Master’s line-signal
detect circuit recognizes this ‘‘wake-up’’ signal the Master
is activated and begins to transmit bursts synchronized as
normal to the MBS or FSa input with a 4 kHz repetition rate
This enables the Slave’s receiver to correctly identify burst
timing from the Master and to re-synchronize its own burst
transmissions to those it receives The flywheel circuits then
acquire full loop sync as described earlier
Loop synchronization is considered to be lost if the flywheel
finds 4 consecutive receive burst ‘‘windows’’ (i e where a
receive burst should have arrived based on timing from pre-
vious bursts) do not contain valid bursts At this point bit C1
in the Status Register is set low the INT output is set low
and the receiver searches to re-acquire loop sync
DIGITAL SYSTEM INTERFACE
The digital system interface on the DASL separates B and D
channel information onto different pins to provide maximum
flexibility On the B channel interface phase skew between
transmit and receive directions may be accommodated at
the Master end since separate frame sync inputs Fsa and
Fsb are provided Each of these synchronizes a counter
which gates the transfer of B1 and B2 channels in consecu-
tive time-slots across the digital interface since the coun-
ters are edge-synchronized the duration of the Fs input sig-
nals may vary from a single-bit pulse to a square-wave The
serial shift rate is determined by the BCLK input and may
be any frequency from 256 kHz to 2 048 MHz as shown in
Figure 6
At the Slave end both Fsa and Fsb are outputs Fsa goes
high for 8 cycles of BCLK coincident with the 8 bits of the
B1 channel in both Transmit and Receive directions Fsb
goes high for the next 8 cycles of BCLK which are coinci-
dent with the 8 bits of the B2 channel in both Transmit and
Receive directions BCLK is also an output at 2 048 MHz
the serial data shift rate as shown in Figure 7 Data may be
exchanged between the B1 and B2 channels as it passes
through the device by setting Control bit C0 e 1 An addi-
tional Frame Sync output FSc is provided to enable a re-
generator to be built by connecting a DASL in Slave Mode
to a DASL in Master Mode The FSc output from the Slave
directly drives the FSa and FSb inputs on the Master
D channel information being packet-mode requires no syn-
chronizing input This interface consists of the transmit data
input Dx receive data output Dr and 16 kHz serial shift
clock DCLK which is an input at the Master end and an
output at the Slave end Data shifts into Dx on falling edges
of DCLK and out from Dr on rising edges as shown in Fig-
ure 11 DCLK should be Synchronous with BCLK
An alternative function of the DCLK DEN pin allows Dx and
Dr to be clocked at the same rate as BCLK at the Master
end only By setting bit C1 in the Control Register to a 1
DCLK DEN becomes an input for an enabling pulse to gate
2 cycles of BCLK for shifting the 2 D bits per frame Thus at
the Master end the D channel bits can be interfaced to a
TDM bus and assigned to a time-slot (the same time-slot for
both transmit and receive) as shown in Figure 12
CONTROL INTERFACE
A serial interface which can be clocked independently from
the B and D channel system interfaces is provided for mi-
croprocessor control of various functions on the DASL de-
vice All data transfers consist of a single byte shifted into
the Control Register via CI simultaneous with a single byte
shifted out from the Status Register via CO see Figure 13
Data shifts in to CI on rising edges of CCLK and out from
CO on falling edges when CS is pulled low for 8 cycles of
CCLK An Interrupt output INT goes low to alert the micro-
processor whenever a change in one of the status bits C1
and or C0 has occurred This latched output is cleared high
following the first CCLK pulse when CS is low No interrupt
is generated when status bit C2 (bipolar violation) goes high
however This bit is set whenever 1 or more violations of the
AMI coding rule is received and cleared everytime the CS is
pulsed Statistics on the line bit error rate can be accumulat-
ed by regularly polling this bit
When reading the CO pin data is always clocked into the
Control Register therefore the CI data word should repeat
the previous instruction if no change to the device mode is
intended
Figure 13 shows the timing for this interface and Table II
lists the control functions and status indicators
5
5 Page 
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
VCC to GND
Voltage at Li Lo
Voltage at any Digital Input
7V
VCCa1V to VSSb1V
VCCa1V to VSSb1V
Storage Temperature Range
Current at Lo
Current at any Digital Output
Lead Temperature (Soldering 10 sec )
ESD (Human Body Model)
b65 C to a150 C
g100 mA
g50 mA
300 C
2000V
Electrical Characteristics Unless otherwise noted limits printed in bold characters are guaranteed for VCC e
5 0V g5% and TA e 0 C to a70 C by correlation with 100% electrical testing at VCC e 5 0V and TA e 25 C All other limits
are assured by correlation with other production tests and or product design and characterization Typical characteristics are
specified at VCC e 5 0V and TA e 25 C All digital signals are referenced to GND
Symbol
Parameter
Conditions
Min Typ Max Units
DIGITAL INTERFACES
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH
Output High Voltage
IIM Input Current at MBS FSc
II Input Current
IOZ Output Current in
High Impedance
State (TRI-STATE )
All Digital Inputs (not MCLK)
All Digital Inputs (not MCLK)
IL e 1 mA
IL e b1 mA
GND k VIN k VCC
Any Other Digital Input GND k VIN k VCC
Br INT TSr CO Dr
GND k VOUT k VCC
22
24
b600
b10
b10
07 V
V
04 V
V
10 mA
10 mA
10 mA
LINE INTERFACES
RLi Input Resistance
CLLo
Load Capacitance
RO Output Resistance
at Lo
VDC Mean d c Voltage
at Lo
POWER DISSIPATION
0V k Li k 5 0V
CLLo from Lo to GND
Load e 60X in Series with 2 mF to GND
Load e 60X in Series with 2 mF to GND
50 kX
100 pF
30 X
20 V
ICC0
ICC1
Power Down Current
Power Up Current (Activated)
Load at Lo e 200X in Series with 2 mF to
GND (in Master Mode)
13 25
20
mA
mA
TRANSMISSION PERFORMANCE
Transmit Pulse Amplitude at Lo
Input Pulse Amplitude at Li
Timing Recovery Jitter
RL e 200X in Series with 2 mF to GND
BCLK at Slave Relative to MCLK at Master
g250
g1 1
100
Vpk
mVpk
ns pk-pk
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TP3406V.PDF ] | |
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