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PDF TP11362 Data sheet ( Hoja de datos )
| Número de pieza | TP11362 | |
| Descripción | Quad Adaptive Differential PCM Processor | |
| Fabricantes | National Semiconductor | |
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March 1997
TP11362A
Quad Adaptive Differential PCM Processor
General Description
The TP11362A is a quad (4) channel Adaptive Differential
Pulse Code Modulation (ADPCM) transcoder, fully compat-
ible to ITU G.726 recommendation in 40 kbps, 32 kbps,
24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11362A
ADPCM processor can operate on up to 8 independent
channels in an 8 kHz frame. Each channel is individually
configured, supporting both full and half duplex operation. All
input/output transfers occur on an interrupt basis using se-
rial, double buffered data registers. Together with National’s
TP3054/57 COMBO® or TP3070/71 COMBO II devices, the
TP11362A forms complete ADPCM channels with Codec/
filtering.
Features
n CCITT G.726 compatible at 40, 32, 24, 16 kbps
n ANSI T1.301 compatible at 32 kbps
n 8-channel half-duplex (encode or decode) or 4-channel
full-duplex operation in 8 kHz frame
n Each channel individually configurable
n Selectable µ-law or A-law PCM coding
n Asynchronous 8 MHz master clock operation
n TTL and CMOS compatible inputs and outputs
n 28-pin PLCC or 24-pin DIP packages
n Power consumption of typ. 6 mW at +5V per full-duplex
channel
n On-Chip Power-On-Reset
n −40˚C to +85˚C operating temperature range
n Single 5V supply
Block Diagram
FIGURE 1. Block Diagram
TRI-STATE® and COMBO® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation DS012877
DS012877-1
www.national.com
1 page  
Functional Description (Continued)
by a receive (decoder) operation. For the encoding opera-
tion, the PCM data is stored in the 8-bit shift register at the
falling edge of CE while TRB is high. The TP11362A pro-
cesses the data within 123 CLK periods during the following
cycle of CE. The encoded ADPCM data is loaded into the
5-bit parallel-to-serial output register with the falling edge of
CE. The MSB data is shifted out first with the leading edge of
CE, and subsequent data is shifted out with the rising edge
of ASCK. For the decoding operation, the ADPCM data is
latched and transferred to the core at the falling edge of CE
while TRB is low. The data is processed within 123 CLK pe-
riods and the decoded 8-bit PCM data is shifted out with the
MSB first.
PSCK and ASCK are the clocks for the PCM and ADPCM
data streams, respectively. They must be high during the
transition of CE. Note that PSCK and ASCK are shown as
gated clocks as an option to conserve power. PSCK and
ASCK need only be valid while CE is high.
FIGURE 3. Serial Output Structure
DS012877-5
5 www.national.com
5 Page 
Timing Specifications (Continued)
Unless otherwise noted, limits
−40˚C to +85˚C by correlation
printed in bold characters are
with 100% electrical testing at
guaranteed
TA = 25˚C.
for VCC = 5.0V ± 5%, GND1 = GND2 = 0V, TA =
All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at VCC = +5V, TA = 25˚C.
Symbol
Parameter
Conditions
Min Typ Max
Units
tHDCEL
Hold Time, CE low after
PSCK/ASCK High
From CE Low
15
ns
tSUCEH
Setup Time, CE High Before
PSCK/ASCK Low
From CE Low
15
ns
tTRBH
tTRBS
tIS
tIH
tPSCK/ASCK
TRB Hold Time
TRB Setup Time
TSI, RSI Setup Time
TSI, RSI Hold Time
PSCK/ASCK High and
Low Times
From CE Low
From ASCK Low and PSCK Low
From ASCK Low and PSCK Low
From ASCK Low and PSCK Low
20
20
20
20
55
ns
ns
ns
ns
ns
tON
TSO, RSO Turn On Time
From CE High
tOD
TSO, RSO Propagation
From ASCK High or PSCK High
Delay Time
40 ns
40 ns
tOFF
TSO, RSO Turn Off Time
From CE Low
(Valid Data to TRI-STATE)
20 ns
tCS
Setup Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
tCH
Hold Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
tRSTL
RSTB Pulse Width Low
2 CLK
Cycles
tRSTH
RSTB High to the First
CE High-Low Transition
6 CLK
Cycles
Note 5: Values for 4 full-duplex (decoding and encoding) or 8 half-duplex (decoding or encoding) channels operation in a 125 µs period.
11 www.national.com
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TP11362.PDF ] | |
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