Datenblatt-pdf.com


TS68882VR20 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer TS68882VR20
Beschreibung CMOS Enhanced Floating-point Co-processor
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 43 Seiten
TS68882VR20 Datasheet, Funktion
Features
Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit
Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit
Signed Exponent)
A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision
Greater than the Extended Precision Format
A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)
Special-purpose Hardware for High-speed Conversion Between Single, Double, and
Extended Formats and the Internal Extended Format
An Independent State Machine to Control Main Processor Communication for
Pipelined Instruction Processing
Forty-six Instructions, Including 35 Arithmetic Operations
Full Conformation to the IEEE 754 Standard, Including All Requirements and
Suggestions
Support of Functions Not Defined by the IEEE Standard, Including a Full Set of
Trigonometric and Transcendental Functions
Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended
Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers
Twenty-two Constants Available In The On-chip ROM, Including π, e, and Powers of 10
Virtual Memory/Machine Operations
Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling
Fully Concurrent Instruction Execution with the Main Processor
Fully Concurrent Instruction Execution of Multiple Floating-point Instructions
Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus
Available in 16.67, 20, 25 and 33 MHz for Tc from -55°C to +125°C
VCC = 5V ± 10%
Description
The TS68882 enhanced floating-point co-processor is a full implementation of the
IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON
TS68000 Family of microprocessors. It is a pin and software compatible upgrade of
the TS68881 with optimized MPU interface that provides over 1.5 times the perfor-
mance of the TS68881. It is implemented using VLSI technology to give systems
designers the highest possible functionality in a physically small device.
Intended primarily for use as a co-processor to the TS68020/68030 32-bit micropro-
cessor units (MPUs), the TS68882 provides a logical extension to the main MPU
integer data processing capabilities. It does this by providing a very high performance
floating-point arithmetic unit and a set of floating-point data registers that are utilized
in a manner that is analogous to the use of the integer data registers. The TS68882
instruction set is a natural extension of all earlier members of the TS68000 Family, and
supports all of the addressing modes of the host MPU. Due to the flexible bus inter-
face of the TS68000 Family, the TS68882 can be used with any of the MPU devices of
the TS68000 Family, and it may also be used as a peripheral to non-TS68000
processors.
Screening/Quality
This product could be manufactured
in full compliance with either:
• MIL-STD-883 Class B
• DESC 5962-89436
• or According to ATMEL-
Grenoble Standards
R suffix
PGA 68
Ceramic Pin Grid Array
F suffix
CQFP 68
Ceramic Quad Flat Pack
CMOS
Enhanced
Floating-point
Co-processor
TS68882
Rev. 2119AHIREL04/02
1






TS68882VR20 Datasheet, Funktion
Signal Summary
Table 1 provides a summary of all the TS68882 signals described in this section.
Table 1. Signal Summary
Signal Name
Address Bus
Data Bus
Size
Address Strobe
Chip Select
Read/Write
Data Strobe
Data Transfer and Size Acknowledge
Reset
Clock
Sense Device
Power Input
Ground
Mnemonic
A0 - A4
D0 - D31
SIZE
AS
CS
R/W
DS
DSACK0, DSACK1
RESET
CLK
SENSE
VCC
GND
Input/Output
Input
Input/Output
Input
Input
Input
Input
Input
Output
Input
Input
Input/Output
Input
Input
Active State
High
High
Low
Low
Low
High/Low
Low
Low
Low
Three State
Yes
Yes
Low No
Detailed
Specifications
Scope
This drawing describes the specific requirements for the microprocessor 68882, 16.67,
20 MHz and 25 MHz, in compliance with MIL-STD-883 class B.
Applicable Documents
MIL-STD-883
1. MIL-STD-883: Test Methods And Procedures For Electronics
2. MIL-PRF-38535 Appendix A: General Specifications For Microcircuits
3. Desc Drawing 5962 - 89436xxx
Requirements
General
The microcircuits are in accordance with the applicable document and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2 and
Figure 2b.
Lead Material and Finish
Lead material and finish shall be any option of MIL-STD-1835.
6 TS68882
2119AHIREL04/02

6 Page









TS68882VR20 pdf, datenblatt
Table 7. AC Electrical Characteristics Read and Write Cycles(1) (Continued)
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)
16.67 MHz
20 MHz
25 MHz
33.33 MHz
N° Parameter
Min Max Min Max Min Max Min Max Unit
22
START false to DSACK0 and DSACK1
high impedance(8)
70 55 55 40 ns
23
START true to clock high (synchronous
read)(3)(8)
0
0
0
0 ns
24
Clock low to data-out valid synchronous
read)(3)
105 80 60 45 ns
25
START true to data-out valid (synchronous
read)(3)(8)
0 105+
80 +
1.5 2.5 1.5 2.5 1.5
60+
2.5
1.5
45- ns
2.5 Clks
26
Clock low to DSACK0 and DSACK1
asserted (synchronous read(3)
75 55 45 30 ns
27
Notes:
START true to DSACK0 and DSACK1
asserted (synchronous read) (3)(8)
75+ 55+ 45+ 30- ns
1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 Clks
1. Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted.
The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear
between 0.8V and 2.0V.
2. These specifications only apply if the TS68882 has completed all internal operations initiated by the termination of the previ-
ous bus cycle when DS was negated.
3. Synchronous read cycles occur only when the save or response CIR locations are read.
4. This specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand CIR can
occur. When the TS68882 is used as a co-processor to the TS68020/68030, this can occur when the addressing mode is
immediate.
5. If the SIZE pin is not strapped to either VCC or GND, it must have the same setup times as do addresses.
6. If the SIZE pin is not strapped to either VCC or GND, it must have the same hold times as do addresses.
7. This number is reduced to 5 nanoseconds if DSACK0 and DSACK1 have equal loads.
8. START is not an external signal; rather, it is the logical condition that indicates the start of an access. The logical equation for
this condition is START = CS + AS + (R/W · DS).
9. If a subsequent access is not a FPCP access, CS must be negated before the assertion of AS and/or DS on the non-FPCP
access. These specifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transi-
tions in CS must not occur simultaneously with transitions of AS or DS. This is not a requirement of the TS68882).
12 TS68882
2119AHIREL04/02

12 Page





SeitenGesamt 43 Seiten
PDF Download[ TS68882VR20 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
TS68882VR20CMOS Enhanced Floating-point Co-processorATMEL Corporation
ATMEL Corporation
TS68882VR25CMOS Enhanced Floating-point Co-processorATMEL Corporation
ATMEL Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche