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PDF TS68882DESC01YA Data sheet ( Hoja de datos )
| Número de pieza | TS68882DESC01YA | |
| Descripción | CMOS Enhanced Floating-point Co-processor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit
Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit
Signed Exponent)
• A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision
Greater than the Extended Precision Format
• A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)
• Special-purpose Hardware for High-speed Conversion Between Single, Double, and
Extended Formats and the Internal Extended Format
• An Independent State Machine to Control Main Processor Communication for
Pipelined Instruction Processing
• Forty-six Instructions, Including 35 Arithmetic Operations
• Full Conformation to the IEEE 754 Standard, Including All Requirements and
Suggestions
• Support of Functions Not Defined by the IEEE Standard, Including a Full Set of
Trigonometric and Transcendental Functions
• Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended
Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers
• Twenty-two Constants Available In The On-chip ROM, Including π, e, and Powers of 10
• Virtual Memory/Machine Operations
• Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling
• Fully Concurrent Instruction Execution with the Main Processor
• Fully Concurrent Instruction Execution of Multiple Floating-point Instructions
• Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus
• Available in 16.67, 20, 25 and 33 MHz for Tc from -55°C to +125°C
• VCC = 5V ± 10%
Description
The TS68882 enhanced floating-point co-processor is a full implementation of the
IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON
TS68000 Family of microprocessors. It is a pin and software compatible upgrade of
the TS68881 with optimized MPU interface that provides over 1.5 times the perfor-
mance of the TS68881. It is implemented using VLSI technology to give systems
designers the highest possible functionality in a physically small device.
Intended primarily for use as a co-processor to the TS68020/68030 32-bit micropro-
cessor units (MPUs), the TS68882 provides a logical extension to the main MPU
integer data processing capabilities. It does this by providing a very high performance
floating-point arithmetic unit and a set of floating-point data registers that are utilized
in a manner that is analogous to the use of the integer data registers. The TS68882
instruction set is a natural extension of all earlier members of the TS68000 Family, and
supports all of the addressing modes of the host MPU. Due to the flexible bus inter-
face of the TS68000 Family, the TS68882 can be used with any of the MPU devices of
the TS68000 Family, and it may also be used as a peripheral to non-TS68000
processors.
Screening/Quality
This product could be manufactured
in full compliance with either:
• MIL-STD-883 Class B
• DESC 5962-89436
• or According to ATMEL-
Grenoble Standards
R suffix
PGA 68
Ceramic Pin Grid Array
F suffix
CQFP 68
Ceramic Quad Flat Pack
CMOS
Enhanced
Floating-point
Co-processor
TS68882
Rev. 2119A–HIREL–04/02
1
1 page  
Figure 2b. CQFP Terminal Designation
TS68882
Functional Signal
Descriptions
This section contains a brief description of the input and output signals for the TS68882
floating-point co-processor. The signals are functionally organized into groups as shown
in Figure 3.
Figure 3. TS68882 Input/output Signals
2119A–HIREL–04/02
Note:
The terms assertion and negation are used extensively. This is done to avoid confusion
when describing “active-low” and “active-high” signals. The term assert or assertion is
used to indicate that a signal is active or true, independent of whether that level is repre-
sented by a high or low voltage. The term negate or negation is used to indicate that a
signal is inactive or false.
5
5 Page 
TS68882
Table 7. AC Electrical Characteristics – Read and Write Cycles(1)
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)
16.67 MHz
20 MHz
25 MHz
33.33 MHz
N° Parameter
6 Address valid to AS asserted(5)
6a Address valid to DS asserted (read)(5)
6b Address valid to DS asserted (write)(5)
7 AS negated to address invalid(6)
7a DS negated to address invalid(6)
Min Max Min Max Min Max Min Max
15 10
5
5
15 10
5
5
50 50 35 26
10 10
5
5
10 10
5
5
8
CS asserted to AS asserted or AS asserted
to CS asserted(9)
0
0
0
0
8a
CS asserted to DS asserted or DS asserted
to CS asserted (read)(9)
0
0
0
0
8b
CS asserted to DS asserted or DS asserted
to CS asserted (write)(9)
30
25
20
15
9 AS negated to CS negated
10 10
5
5
9a DS negated to CS negated
10 10
5
5
10 R/W high to AS asserted (read)
15 10
5
5
10a R/W high to DS asserted (read)
15 10
5
5
10b R/W low to DS asserted (write)
35 30 25 25
11
AS negated to R/W low (read) or
AS negated to R/W high (write)
10 10
5
5
11a
DS negated to R/W low (read) or
DS negated to R/W high (write)
10 10
5
5
12 DS width asserted (write)
40 38 30 23
13 DS width negated
40 38 30 23
13a DS negated to AS asserted(4)
30 30 25 18
14 CS, DS asserted to data-out valid (read)(2) 80 45 45 30
15 DS negated to data-out invalid (read)
0
0
0
0
16
DS negated to data-out high impedance
(read)
50 35 35 30
17 Data-in invalid to DS asserted (write)
15
10
5
5
18 DS negated to data-in invalid (write)
15
10
5
5
19
START true to DSACK0 and DSACK1
asserted(2)
50 35 25 20
19a
DSACK0 asserted to DSACK1 asserted
(skew)(7)
-15 15 -10 10 -10 10
5
20
DSACK0 or DSACK1 asserted to data-out
valid
50
43
32
17
21
START false to DSACK0 and DSACK1
negated(8)
50 30 40 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2119A–HIREL–04/02
11
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet TS68882DESC01YA.PDF ] | |
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