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TS68302VA16 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer TS68302VA16
Beschreibung Integrated Multiprotocol Processor IMP
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 47 Seiten
TS68302VA16 Datasheet, Funktion
Features
TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family
System Integration Block Including:
– Independent Direct Memory Access (IDMA) Controller
– Interrupt Controller with Two Modes of Operation
– Parallel Input/output (I/O) Ports, some with Interrupt Capability
– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
– Three Timers, including a Watchdog Timer
– Four Programmable Chip-select Lines with Wait-state Logic
– Programmable Address Mapping of Dual-port RAM and IMP Registers
– On-chip Clock Generator with an Output Clock Signal
– System Control:
System Control Register
Bus Arbitration Logic with Low Interrupt Latency Support
Hardware Watchdog for Monitoring Bus Activity
Low Power (Standby) Modes
Disable CPU Logic (TS68000)
Freeze Control for Debugging Selected On-chip Peripherals
DRAM Refresh Controller
Communications Processor Including:
– Main Controller (RISC Processor)
– Three Full-duplex Serial Communication Controllers (SCCs)
– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)
General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and
Nonmultiplexed Serial Interface (NMSI) Operation
– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up
to 4.096 MHz
– Serial Management Controllers (SMCs) for IDL and GCI Channels
Frequency of Operation: 16.67 MHz
Power Supply: 5 VDC ± 10%
Description
The IMP is a very large-scale integration (VLSI) device incorporating the main building
blocks needed for the design of a wide variety of controllers. The device is especially
suitable to applications in the communications industry. The IMP is the first device to
offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 micro-
processor core and a flexible communications architecture. This multichannel
communications device may be configured to support a number of popular industry
interfaces, including those for the integrated services digital network (ISDN) basic rate
and terminal adapter applications. Through a combination of architectural and pro-
grammable features, concurrent operation of different protocols is easily achieved
using the IMP. Data concentrators, line cards, bridges, and gateways are examples of
suitable applications for this versatile device.
The IMP is a high-density complementary metal-oxide semiconductor (HCMOS)
device consisting of a TS68000/TS68008 microprocessor core, a system integration
block (SIB), and a communications processor (CP). The TS68302 block diagram is
shown in Figure 1.
Note: GCI is sometimes referred to as IOM2.
Integrated
Multiprotocol
Processor (IMP)
TS68302
Rev. 2117A–HIREL–11/02
1






TS68302VA16 Datasheet, Funktion
Signal Descriptions
The input and output signals of the TS68302 are organized into functional groups as
shown in Table 1. Refer to TS68302 Integrated Multiprotocol Processor User’s Manual,
for detailed information on the TS68302 signals.
Table 1. Signal Definitions
Functional Group
Clocks
System Control
Address Bus
Data Bus
Bus Control
Bus Control
Bus Arbitration
Interrupt Control
NMSI1/ISDN I/F
NMSI2/PIO
NMSI3/SCP/PIO
IDMA/PAIO
IACK/PBIO
Timer/PBIO
PBIO
Chip Select
Testing
VDD
GND
Signals
XTAL, EXTAL, CLKO
RESET, HALT, BERR, BUSW, DISCPU
A23-A1
D15-D0
AS, R/W, UDS/A0, LDS/DS, DTACK
RMC, IAC, BCLR
BR, BG, BGACK
IPL2-IPL0, FC2-FC0, AVEC
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, BRG1
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, SDS2
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, PA12
DREQ, DACK, DONE
IACK7, IACK6, IACK1
TIN2, TIN1, TOUT2, TOUT1, WDOG
PB11-PB8
CS3-CS0
FRZ (2 Spare)
Power supply
Ground connection
Number
3
5
23
16
5
3
3
7
8
8
8
3
3
5
4
4
3
8
13
Scope
Applicable
Documents
MIL-STD-883
Requirements
General
This drawing describes the specific requirements for the processor TS68302, 16.67
MHz, in compliance either with MIL-STD-883 class B or with Atmel standards.
1. MIL-STD-883: test methods and procedures for electronics.
2. MIL-M-38535: general specifications for microcircuits.
3. Desc Drawing: 5962-93159 (planned).
The microcircuits are in accordance with the applicable document and as specified
herein.
6 TS68302
2117A–HIREL–11/02

6 Page









TS68302VA16 pdf, datenblatt
Dynamic (Switching)
Characteristics
The limits and values given in this section apply over the full case temperature range -
55°C to +125°C or -40°C to +85°C depending on selection see “Ordering Information”
on page Reference 2 and VCC in the range 4.5V to 5.5V VIL = 0.5V and VIH = 2.4V.
The INTERVAL numbers (NUM) refer to the timing diagrams. See Figure 6 to Figure 25.
The AC specifications presented consist of output delays, input setup and hold times,
and signal skew times. All signals are specified relative to an appropriate edge of the
clock (CLKO pin) and possibly to one or more other signals.
Figure 6. Clock Timing Diagram
VCIH = 4V
EXTAL
VCIL = 0.6V
1
2
3
54
5a 5a
CLKO
Table 7. AC Electrical Specifications - Clock Timing (see Figure 7)
Num.
Symbol Parameter
Min Max Unit
f Frequency of Operation
8
16.67
MHz
1 tcyc Clock Period (EXTAL)
60 125 ns
2, 3
tCL, tCH
Clock Pulse Width (EXTAL)
25 62.5 ns
4, 5
tCr, tCf
Clock Rise and Fall Times (EXTAL)
5 ns
5a tCD EXTAL to CLKO delay(1)(2)
2 11 ns
Notes: 1. CLKO loading is 50 pF max.
2. CLKO skew from the rising and falling edges of EXTAL will not differ from each other more than 1 ns, if the EXTAL rise time
equals the EXTAL fall time.
12 TS68302
2117A–HIREL–11/02

12 Page





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