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TS68020DESC02XC Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer TS68020DESC02XC
Beschreibung HCMOS 32-bit Virtual Memory Microprocessor
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 45 Seiten
TS68020DESC02XC Datasheet, Funktion
Features
Object Code Compatible with Earlier TS68000 Microprocessors
Addressing Mode Extensions for Enhanced Support of High Level Languages
New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882
Floating Point Co-processors
Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple
Instructions to be Executed Concurrently
High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals
Full Support of Virtual Memory and Virtual Machine
Sixteen 32-bit General-purpose Data and Address Registers
Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
18 Addressing Modes and 7 Data Types
4-Gbyte Direct Addressing Range
Processor Speed: 16.67 MHz - 20 MHz - 25 MHz
Power Supply: 5.0 VDC ± 10%
Description
The TS68020 is the first full 32-bit implementation of the TS68000 family of micropro-
cessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers
and data paths, 32-bit addresses, a rich instruction set, and versatile addressing
modes.
HCMOS 32-bit
Virtual Memory
Microprocessor
TS68020
Screening/Quality
This product is manufactured in full compliance with either:
• MIL-STD-883 (class B)
• DESC 5962 - 860320
• or according to Atmel standards
See “Ordering Information” on page 43.
Pin connection: see page 3.
R suffix
PGA 114
Ceramic Pin Grid Array
F suffix
CQFP 132
Ceramic Quad Flat Pack
Rev. 2115A–HIREL–07/02
1






TS68020DESC02XC Datasheet, Funktion
Detailed
Specifications
Scope
This drawing describes the specific requirements for the microprocessor 68020,
16.67 MHz, 20 MHz and 25 MHz, in compliance with the MIL-STD-883 class B.
Applicable
Documents
MIL-STD-883
• MIL-STD-883: Test Methods and Procedures for Electronics
• MIL-PRF-38535 appendix A: General Specifications for Microcircuits
• Desc Drawing 5962 - 860320xxx
Requirements
General
The microcircuits are in accordance with the applicable document and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2 and
Figure 3.
Lead Material and Finish
Lead material and finish shall be any option of MIL-STD-1835.
Package
The macrocircuits are packages in hermetically sealed ceramic packages which are
conform to case outlines of MIL-STD-1835 (when defined):
• 114-pin SQ.PGA UP PAE Outline
• 132-pin Ceramic Quad Flat Pack CQFP
The precise case outlines are described on Figure 23 and Figure 24.
6 TS68020
2115A–HIREL–07/02

6 Page









TS68020DESC02XC pdf, datenblatt
Table 6. Dynamic Electrical Characteristics (Continued)
Symbol
tDVSA
tDICL
tBELCL
tSNDN
tSNDI
tSNDIZ
tDADI
tDADV
tHRrf
tCLBA
tCLBN
tBRAGA
tGAGN
tGABRN
tGN
tGA
tCHDAR
tCLDNR
tCLDAW
tCHDNW
tRADA
tDA
tRWA
tAIST
tAIHT
tDABA
tDOCH
tBNHN
Parameter
Data Out Valid to DS Asserted (Write)
26
Data in Valid to Clock Low (Data Setup)
Late BERR/HALT Asserted to Clock
Low Setup Time
AS, DS Negated to
DSACKx/BERR/HALT/AVEC Negated
DS Negated to Data On Invalid (Data in
Hold Time)
DS Negated to Data in High Impedance
DSACKx Asserted to Data In Valid
DSACK Asserted to DSACKx Valid
(DSACK Asserted Skew)
RESET Input Transition Time
Clock Low to BG Asserted
Clock Low to BG Negated
BR Asserted to BG Asserted (RMC Not
Asserted)
BGACK Asserted to BG Negated
BGACK Asserted to BR Negated
BG Width Negated
BG Width Asserted
Clock High to DBEN Asserted (Read)
Clock Low to DBEN Negated (Read)
Clock Low to DBEN Negated (Read)
Clock High to DBEN Asserted (Read)
R/W Low to DBEN Asserted (Write)
DBEN Width Asserted
READ
WRITE
R/W Width Asserted (Write or Read)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACKx Asserted to BERR/HALT
Asserted
Data Out Hold from Clock High
BERR Negated to HALT Negated
(Rerun)
Interval
Number
26
27
27A
28
29
29A
31
31A
32
33
34
35
37
37A
39
39A
40
41
42
43
44
45
46
47A
47B
48
53
68020-16
Min Max
15
5
20
0 80
0
60
50
15
1.5
0 30
0 30
1.5 3.5
1.5 3.5
0 1.5
90
90
0 30
0 30
0 30
0 30
15
60
120
150
5
15
30
0
0
68020-20
Min Max
10
68020-25
Min Max
5
55
15 10
0 65 0 50
00
50 40
43 32
10 10
1.5 1.5
0 25 0 20
0 25 0 20
1.5 3.5 1.5 3.5
1.5 3.5 1.5 3.5
0 1.5 0 1.5
75 60
75 60
0 25 0 20
0 25 0 20
0 25 0 20
0 25 0 20
10 10
50 40
100 80
125 100
55
15 10
20 18
00
00
Unit
ns
ns
ns
ns
ns
ns
ns
Clks
ns
ns
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(6)
(6)
(2)(11)
(3)(11)
(11)
(11)
(11)
(11)
(6)
(5)
(5)
(11)
(11)
(4)(11)
12 TS68020
2115A–HIREL–07/02

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