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PDF TR3100 Data sheet ( Hoja de datos )
| Número de pieza | TR3100 | |
| Descripción | 433.92 MHz Hybrid Transceiver | |
| Fabricantes | RF Monolithics Inc | |
| Logotipo |  |
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®
· Designed for Short-Range Wireless Data Communications
· Supports RF Data Transmission Rates Up to 576 kbps
· 3 V, Low Current Operation plus Sleep Mode
· Stable, Easy to Use, Low External Parts Count
The TR3100 hybrid transceiver is ideal for short-range wireless data applications where robust
operation, small size, low power consumption and low cost are required. The TR3100 employs
RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of character-
istics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in.
The receiver section of the TR3100 is sensitive and stable. A wide dynamic range log detector,
in combination with digital AGC and a compound data slicer, provide robust performance in the
presence of on-channel interference or noise. Two stages of SAW filtering provide excellent re-
ceiver out-of-band rejection. The TR3100 is optimized for RF data rates from 230.4 to 576 kbps
using amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to sup-
press output harmonics, facilitating compliance with ETSI I-ETS 300 220 and similar regulations.
TR3100
433.92 MHz
Hybrid
Transceiver
Absolute Maximum Ratings
Rating
Power Supply and All Input/Output Pins
Non-Operating Case Temperature
Soldering Temperature (10 seconds)
Value
-0.3 to +4.0
-50 to +100
250
Units
V
oC
oC
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC)
Characteristic
Sym Notes
Operating Frequency
Modulation Type
fO
Data Rate
Receiver Performance, High Sensitivity Mode
Sensitivity, 230.4 kbps, 10-3 BER, AM Test Method
1
Sensitivity, 230.4 kbps, 10-3 BER, Pulse Test Method
1
Current, 230.4 kbps
Sensitivity, 460.8 kbps, 10-3 BER, AM Test Method
1
Sensitivity, 460.8 kbps, 10-3 BER, Pulse Test Method
1
Current, 460.8 kbps
Sensitivity, 576 kbps, 10-3 BER, AM Test Method
1
Sensitivity, 576 kbps, 10-3 BER, Pulse Test Method
1
Current, 576 kbps
Receiver Out-of-Band Rejection, ±5% fO
Receiver Ultimate Rejection
R±5%
RULT
2
2
Minimum
433.72
Typical
ASK
-96
-90
5.8
-93
-87
6.5
-91
-85
7.0
70
90
Maximum
434.12
Units
MHz
576 kbps
dBm
dBm
mA
dBm
dBm
mA
dBm
dBm
mA
dB
dB
1
1 page  
A n te n n a
R F IO
20
T u n in g
SAW
C R F ilte r
T u n in g /E S D
TX C N C N
IN T R L 1 T R L 0
TXM O D
R TXM
8 17
18
M o d u la tio n
& B ia s C o n tr o l
TXA2 TXA1
A S H T r a n s c e iv e r B lo c k D ia g r a m
P ow erD ow n
C o n tro l
Log
V C C 1 : P in 2
V C C 2 : P in 1 6
G N D 1 : P in 1
G N D 2 : P in 1 0
G N D 3 : P in 1 9
R R E F : P in 1 1
C M P IN : P in 6
BBO UT
R FA1
SAW
D e la y L in e
R FA2
D e te c to r
L o w -P a s s
F ilte r
BB
5
P eak R ef
6 D e te c to r
C BBO
LP FA D J 9
PKDET 4
C PKD
R LPF
DS2
d B B e lo w
P e a k T h ld
AND 7
A G C S et
G a in S e le c t
P u ls e G e n e r a to r
& R F A m p B ia s
P R A TE 14
1 5 P W ID T H
R PR R PW
AG C
C o n tro l
AG CCAP 3
C AGC
A G C R eset
AG C DS1
R e f T h ld
T h r e s h o ld
C o n tro l
TH LD 1
13
R TH1
11 12
R TH2
R REF
TH LD 2
R XD ATA
Figure 2
the start of the next RFA1 ON sequence should be set to sample
the narrowest RF data pulse at least 10 times. Otherwise, significant
edge jitter will be added to the detected data pulse.
ASH Transceiver Block Diagram
Figure 2 is the general block diagram of the ASH transceiver.
Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the transceiver are
the antenna and its matching components. Antennas presenting an
impedance in the range of 35 to 72 ohms resistive can be satisfacto-
rily matched to the RFIO pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be
matched using two or three components. For some impedances,
two inductors and a capacitor will be required. A DC path from RFIO
to ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier in-
cludes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain Se-
lect). AGC Set is an input to the AGC Control function, and Gain Se-
lect is the AGC Control function output. ON/OFF control to RFA1
(and RFA2) is generated by the Pulse Generator & RF Amp Bias
function. The output of RFA1 drives the SAW delay line, which has
a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below satura-
tion. The output of RFA2 drives a full-wave detector with 19 dB of
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is
added to the output of the full-wave detector to produce an overall
detector response that is square law for low signal levels, and tran-
sitions into a log response for high signal levels. This combination
provides excellent threshold sensitivity and more than 70 dB of
detector dynamic range. In combination with the 30 dB of AGC
range in RFA1, more than 100 dB of receiver dynamic range is
achieved.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re-
sistor.
The filter is followed by a base-band amplifier which boosts the de-
tected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
For lower duty cycles, the mV/dB slope and peak-to-peak signal
level are proportionately less. The detected signal is riding on a
1.1 Vdc level that varies somewhat with supply voltage, tempera-
ture, etc. BBOUT is coupled to the CMPIN pin or to an external data
recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
and other factors as discussed in the ASH Transceiver Designer’s
Guide.
When an external data recovery process is used with AGC, BBOUT
must be coupled to the external data recovery process and CMPIN
by separate series coupling capacitors. The AGC reset function is
driven by the signal applied to CMPIN.
When the transceiver is placed in power-down (sleep) or in a trans-
mit mode, the output impedance of BBOUT becomes very high. This
feature helps preserve the charge on the coupling capacitor to mini-
mize data slicer stabilization time when the transceiver switches
back to the receive mode.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog
signal from BBOUT back into a digital stream. The best data slicer
choice depends on the system operating parameters. Data slicer
DS1 is a capacitively-coupled comparator with provisions for an ad-
justable threshold. DS1 provides the best performance at low
5
5 Page 
Pin Name
Description
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON
pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON
pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The
value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
15 PWIDTH A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifi-
ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.
VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be by-
16
VCC2
passed with an RF capacitor, and must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. See
the ASH Transceiver Designer’s Guide for additional information.
CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in
the receive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode (TR3100). CNTRL1
low and CNTRL0 high place the unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in
17
CNTRL1
the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to
300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An
input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum
source current of 40 µA. A logic low requires a maximum sink current of 25 µA (1 µA in sleep mode). This pin
must be held at a logic level; it cannot be left unconnected.
CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a
high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input
18
CNTRL0
voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
should not be applied to this pin. A logic high requires a maximum source current of 40 µA. A logic low requires a
maximum sink current of 25 µA (1 µA in sleep mode). This pin must be held at a logic level; it cannot be left un-
connected.
19
GND3
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-
20
RFIO
ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to
ground is required for ESD protection.
.4 3 5
0 .0 0 0
D im e n s io n s in in c h e s .
S M -2 0 H P C B P a d L a y o u t
.3 7 0
.3 4 5
.3 0 5
.2 6 5
.2 2 5
.1 8 5
.1 4 5
.1 0 5
.0 9
.0 6 5
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet TR3100.PDF ] | |
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