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PDF TQ9502 Data sheet ( Hoja de datos )
| Número de pieza | TQ9502 | |
| Descripción | 531/1063 Mbaud Fibre Channel Transmitter and Receiver | |
| Fabricantes | TriQuint Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TQ9502 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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TRIQUINT
S E M I C O N D U C T O R, I N C .
Data
32
Parity
4
Control
11
HOST
Data
32
Parity
4
Control
12
Data
10
Control
2
TQ9303
ENDEC
Data
10
Control
2
TQ9501
Transmitter
TQ9502
Receiver
Optical Tx
2 or Copper
Interface
2
Fiber
2 Optic
Cable
2
Optical Rx
2 or Copper
Interface
TQ9501/9502
531/1063 Mbaud
Fibre Channel
Transmitter and
Receiver
TriQuint’s Fibre Channel transmitter (TQ9501) and receiver (TQ9502) are
part of the FC531/FC1063 (Fibre Channel 531 and 1063 Megabaud) chip
set. In addition to the transmitter and receiver, TriQuint offers the ENcoder/
DECoder (TQ9303 ENDEC). The TQ9501, TQ9502, TQ9303 and a gigabit
fiber optic module set provide a complete solution for Fibre Channel's FC0
and FC1 layers as well as partial support for the FC2 layer.
The TQ9501 and TQ9502 are designed in TriQuint's proprietary 0.7-micron
GaAs process, enabling the transmitter and receiver to run at higher speeds
and lower power than with conventional processes. The transmitter and
receiver data interface has been selected to be 10 bits in order to conserve
input/output power and to reduce pin count and package size. The trans-
mitter performs the parallel-to-serial conversion and generates the internal
high-speed clock for the serial output. The receiver performs serial-to-
parallel conversion, recovers the clock and data from the serial input, and
detects the K28.5 character (Fibre Channel standard “SYNC” transmission
character).
The TQ9303 ENDEC implements 8b/10b encoding and decoding, ordered
set encoding and decoding, parity checking and generation, 32-bit CRC
checking and generation, and word synchronization as defined in the
Fibre Channel Physical and Signaling Interface Standard (FC-PH).
Fibre Channel provides a high-speed physical layer for Intelligent
Peripheral Interface (IPI) and Small Computer System Interface (SCSI)
upper-layer command sets, High-Performance Parallel Interface (HIPPI)
data link layer, and other user-defined command sets. Fibre Channel
replaces the SCSI, IPI and HIPPI physical interfaces with a higher-
speed interface capable of driving longer distances.
Features
• Compliant with ANSI X3T11
Fibre Channel Standard
• Operates at 531.125 Mbaud
and 1.0625 Gigabaud
(1.25 Gigabaud max)
• Low power dissipation
(2.25 W, typical)
• Low jitter
• No external PLL components
• 10-bit TTL-compatible data bus
• Synchronous Data Bus Interface
• Direct interface to TQ9303 ENDEC
• Single +5 V supply
• 48-pin MQuad package
For additional information and latest specifications, see our website: www.triquint.com
1
1 page  
TQ9501/TQ9502
Figure 3. System Block Diagram – Fibre Channel
Host
RATESEL
REFCLK
LOOPEN
TQ9501 TX
SIGDET
TQ9303 ENDEC
CTXD0..31 BTXD0..9
CTXC0,1 BTXCKOUT
CTXP0..3 BTXCKIN
CTXRAWA,B
CTXRAW
CTXPENN
CTXPMODE
CTXPERR
CTXCERR
CTXCLK
CTXWREF
TX, TY
TXD0..9 TLX, TLY
TXCLK
BYTECLK
RATESEL
REFCLK
LOOPEN
SIG, SIGN
RESETN
CRXD0..31
CRXP0..3
CRXS0..5
RAWRX
RXPMODE
BRXD0..9
BRXCLK
BRXSYNC
WRDSYNCN
RXCKPH0,1
CRXCLK
TQ9502 RX
RXD0..9
RXCLK
SYNC
RLX, RLY
2
RX, RY
2
RTX
RTY
SYNCEN
CLKPOL
RLTX
RLTY
Optical,
Coaxial, or
Twisted Pair
Interface
Out
Optical,
Coaxial, or
Twisted Pair
Interface
In
Termination
Network
Note that the fast edge rates of the TQ9303 TX bus
outputs can affect the stability of the TQ9501 PLL.
These edge rates can be effectively “slowed” by adding
some series resistance of from 90 to 250 ohms to the
TX data bus lines (TXD0..9) as shown in Figure 4.
Resistance should also be added to TXCLK to maintain
the correct timing relationship with the data lines. The
resistors should be placed near the TQ9303.
Figure 4. Adding resistance and capacitance to
the TX data bus.
TQ9303
TQ9301
In cases where the line capacitance of the bus traces is
less than 3 pF, it may also be necessary to add from
1– 2 pf of capacitance to each trace near the TQ9501.
The purpose is to slow the edge rates enough to
prevent potential undershoot from disturbing the power
supplies in the PLL circuitry of the TQ9501.
For additional information and latest specifications, see our website: www.triquint.com
5
5 Page 
TQ9501/TQ9502
Table 12. AC Specifications—TQ9501 Transmitter
Parameters with dual values refer to 531Mbaud/1063Mbaud operation respectively.
Parameter
Description
Min. Typ.
T1 REFCLK pulse width HIGH
10.0
T2 REFCLK pulse width LOW
10.0
T31 REFCLK period (T)
32.0
T4 TXD 9..0 setup time
2.0
T5 TXD 9..0 hold time
2.0
T6 BYTECLK, TXCLK pulse width HIGH
6.0/3.0
T7 BYTECLK, TXCLK pulse width LOW
6.0/3.0
T8 BYTECLK, TXCLK period (T)
16.0/8.0
T9 TX, TY, TLX, TLY rise time
100
T10 TX, TY, TLX, TLY fall time
100
T11 TX ~ TY or TLX ~ TLY skew
T123 TX , TY or TLX , TLY output jitter – deterministic jitter (DJ)
– random jitter (RJ)
Notes: 1. REFCLK Tolerance = (20/baud rate) ±0.01%, for baud rate of 500Mbaud to 625Mbaud and
(40/baud rate) ± 0.01%, for baud rate of 1 Gbaud to 1.25 Gbaud.
2. baud time = 1/baud rate
3. The jitter numbers are for a BER of 10–12.
Figure 8. Bus Timing – TQ9501 Transmitter
Max.
40.0
20.0/10.0
400/300
400/300
100/60
100/75
200/150
REFCLK
TXD0..9
TXCLK
BYTECLK
T4
T6
Figure 9.Serial Output Timing – TQ9501
TX, TLX
T12
T9
T1
T3
T5
T7
T8
T10
T12
T2
T11
80%
50%
20%
TY, TLY
T12
T12
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
For additional information and latest specifications, see our website: www.triquint.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TQ9502.PDF ] | |
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