PDF TQ8105 Data sheet ( Hoja de datos )

Número de pieza	TQ8105
Descripción	SONET/SDH Transceivers
Fabricantes	TriQuint Semiconductor
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No Preview Available ! TRIQUINT S E M I C O N D U C T O R, I N C . SONET/SDH Overhead Processor Reference Clock TQ8105 or TQ8106 SONET/SDH Transceiver Rx O/E with CDR Tx O/E SONET/SDH Overhead Processor TQ8106 SONET/SDH Transceiver with CDR Rx O/E Tx O/E The TQ8105/TQ8106 are SONET/SDH transceivers that integrate multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and enhanced line and clock diagnostic functions into a single monolithic device. The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow maximum flexibility in the selection of internal/external Clock and Data Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources. On-chip PLLs use external RC-based loop filters to allow custom tailoring of loop response and support the wide range of reference clock frequencies found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR, the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems when combined with industry-typical O/E devices such as Sumitomo, AT&T, HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant- rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing clocking for UTOPIA and other system busses. Transmit data may also be clocked into the devices with respect to the reference clock. Operating from a single +5V supply, the TQ8105/TQ8106 provides fully compliant functionality and performance, utilizing direct-connected PECL levels (differential or single-ended) for high-speed I/O. As compared to AC- coupled schemes, the direct-coupled connections reduce jitter and switching-level offsets due to data patterns. The TQ8105/TQ8106 can also provide direct connection to high-speed I/O utilizing ECL levels with a –5V supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/ PECL reference clock input is also provided; at 155.52 MHz the input should be only PECL/ECL.) Output TTL pins can be tristated and may also be configured for VOH with a 3.3V supply connection. TQ8105/8106 PRELIMINARY DATA SHEET SONET/SDH Transceivers Features • Single-chip, byte-wide Mux, Demux, Framer, and Tx clock- synthesis PLL with enhanced diagnostics • TQ8106 includes monolithic Clock and Data Recovery • SONET/SDH/ATM compliant for STS-12/STM-4 (622 Mb/s) or STS-3/STM-1 (155 Mb/s) rates • 155.52, 77.76, 51.84, 38.88, or 19.44 MHz reference clock inputs with TTL, PECL, or ECL level • 38.88 MHz and 51.84 MHz clock outputs for UTOPIA as well as byte clock rate (77.76 or 19.44 MHz) • External RC-based loop filters • Integrated loopbacks with enhanced line and reference clock diagnostics • Direct-coupled standard, PECL, high-speed I/O with ECL option • Clean TTL interface to PMC-Sierra devices • 100-pin 14x14 mm JEDEC plastic package • +5V-only supply for PECL I/O (–5.2V required for ECL I/O option) • –40 to +125°C case operating temperature For additional information and latest specifications, see our website: www.triquint.com 1 1 page TQ8105/TQ8106 PRELIMINARY DATA SHEET Table 1. Signal Descriptions (continued) Pin Signal Function Description 16 DVPP Ground/+5V ECL/PECL Driver Return (see Table 6B) 17 RXCKP ECL/PECL Input Receive Clock, True (Ignored when CDR used) 18 RXCKN ECL/PECL Input Receive Clock, Complement (Ignored when CDR used) 19 DVPP Ground/+5V ECL/PECL Driver Return (see Table 6B) 20 VPP Ground/+5V ECL/PECL Positive Supply (see Table 6B) 21 NSOL ECL/PECL Input Loss of Signal — zeroes serial data in when low; RXBC=TXCK/8 22 VNN –5.2V/Ground ECL/PECL section power (see Table 6B) 23 NC/CDRFP1* Analog Output CDR Loop Filter Pin 1 — Charge Pump Out (ignored by TQ8105) 24 NC/CDRFP2* Analog Input CDR Loop Filter Pin 2 — VCO Tune (ignored by TQ8105) 25 GND GND Core Ground 26 SVDD +5V Output Driver Internal Positive Supply 27 VDD +5V Core Positive Supply 28 CDRAVDD* Analog +5V TQ8106 CDR Analog +5V Supply (not connected if CDR not used; ignored by TQ8105) 29 VCC +5V/+3.3V TTL Driver Positive Supply 30 RxBC Tristate TTL Out Demultiplexer Byte Clock 31 DGND GND TTL Driver Ground 32 DXSYNC Tristate TTL Out Frame Synchronization Signal 33 VCC +5V/+3.3V TTL Driver Positive Supply 34 DXD0 Tristate TTL Out Demultiplexer Data Bit 0 (LSB) 35 DGND GND TTL Driver Ground 36 DXD1 Tristate TTL Out Demultiplexer Data Bit 1 37 VCC +5V/+3.3V TTL Driver Positive Supply 38 DXD2 Tristate TTL Out Demultiplexer Data Bit 2 39 DGND GND TTL Driver Ground 40 DXD3 Tristate TTL Out Demultiplexer Data Bit 3 41 VCC +5V/+3.3V TTL Driver Positive Supply 42 DXD4 Tristate TTL Out Demultiplexer Data Bit 4 43 DGND GND TTL Driver Ground 44 DXD5 Tristate TTL Out Demultiplexer Data Bit 5 45 VCC +5V/+3.3V TTL Driver Positive Supply 46 DXD6 Tristate TTL Out Demultiplexer Data Bit 6 47 DGND GND TTL Driver Ground 48 DXD7 Tristate TTL Out Demultiplexer Data Bit 7 (MSB) 49 SVDD +5V Output Driver Internal Positive Supply 50 VDD +5V Core Positive Supply 51 NC/CDRGND* GND GND for TQ8106 to powerup CDR (ignored by TQ8105) 52 GND GND Core Ground 53 FRPWR TTL Input Framer Power Control (power on when high) 54 OOF TTL Input Out-of-Frame: Initiates Frame Search/Bit Alignment 55 VCC +5V/+3.3V TTL Driver Positive Supply 56 LOS Tristate TTL Output Loss of Signal (high when > 128 bit periods without transitions) 57 DGND GND TTL Driver Ground Note: TQ8106-specific signal For additional information and latest specifications, see our website: www.triquint.com 5 5 Page TQ8105/TQ8106 PRELIMINARY DATA SHEET Table 2A. TQ8105/TQ8106 Recommended Transmit Loop Filter Values (Preliminary) Reference Frequency (MHz) 19.44 38.88 51.84 77.76 155.52 Divide Ratio 32 16 12 8 4 Note: *Internal divide by two on Reference Resistor Value R1 (ohms) 1200 620 470 300 300 Capacitor Value C1 (µF) 0.082 0.15 0.22 0.33 0.33 Capacitor Value C2 (pF) 82 150 220 330 330 Table 2B. TQ8106 Recommended CDR Loop Filter Values (Preliminary) Incoming NRZ Data Rate (Mbs) 155.52 622.08 Resistor Value R2 (ohms) 470 680 Capacitor Value C3 (µF) 1.0 4.7 Capacitor Value C4 (pF) 39 39 AVDD FP1 FP2 C2 CDRAVDD C1 R1 CDR FP 1 CDR FP 2 C4 C3 R2 Figure 5. Loopback Modes RXD RXCK TXD TXCK Normal DXD RXBC MXD RXD RXCK TXD TXCK Split DXD RXBC MXD Equipment RXD RXCK DXD RXBC TXD TXCK MXD RXD RXCK TXD TXCK Facility DXD MXD For additional information and latest specifications, see our website: www.triquint.com 11 11 Page

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