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PDF TQ1089 Data sheet ( Hoja de datos )
| Número de pieza | TQ1089 | |
| Descripción | 11-Output Configurable Clock Buffer | |
| Fabricantes | TriQuint Semiconductor | |
| Logotipo |  |
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TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
TQ1089
FBIN GND REFCLK GND GND GND GND
11 10 9 8 7 6 5
TEST 12
VDD 13
Q0 14
GND 15
Q1 16
Q2 17
VDD 18
Phase
Detector
VCO
MUX
Divide Logic
÷2
Output Buffers Group B
Group A
4 VDD
3 Q10
2 Q9
1 GND
28 Q8
27 Q7
26 VDD
19 20
GND Q3
21 22 23
Q4 VDD Q5
24 25
Q6 GND
TriQuint’s TQ1089 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 65 MHz to 90
MHz and from 130 MHz to 180 MHz. The outputs are available at either 1x
and 2x or at 1x and 1/2 x the reference clock frequency, fREF . When one of
the Group A outputs (Q0–Q8) is used as feedback to the PLL, all Group A
outputs will be at fREF , and all Group B outputs (Q9, Q10) will be at 2x fREF
. When one of the Group B outputs is used as feedback to the PLL, all
Group A outputs will be at 1/2 x fREF and all Group B outputs will be at fREF .
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. This completely self-contained PLL requires no external
capacitors or resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a
frequency range from 260 MHz to 360 MHz. By feeding back one of the
output clocks to FBIN, the PLL continuously maintains frequency and
phase synchronization between the reference clock (REFCLK) and each of
the outputs.
11-Output
Configurable
Clock Buffer
Features
• Wide frequency range:
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
eight outputs at fREF
two outputs at 2x fREF or
nine outputs at 1/2 x fREF
one output at fREF
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps + 500 ps (max) or
–350 ps +700 ps (max)
• TTL–compatible with 30 mA
output drive
• 28–pin J–lead surface–mount
package
• Ideal for PowerPC ™–based
designs
TriQuint’s patented output buffer design delivers a very low output-to-
output skew of 150 ps (max). The TQ1089’s symmetrical TTL outputs are
capable of sourcing and sinking 30 mA.
For additional information and latest specifications, see our website: www.triquint.com
1
1 page  
TQ1089
AC Characteristics
(VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
t CPWH
t CPWL
t IR
Input Clock (REFCLK)
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V - 2.0V)
Test Conditions (Figure 3) 1
Figure 4
Figure 4
Min Typ Max Unit
3 --- — ns
3 --- — ns
— — 2.0 ns
Symbol
t OR,t OF
t PD1 2
t PD2 2
t SKEW1 3
t SKEW2 3
t SKEW3 3
t SKEW4 3
t CYC 4
t JP 5
t JR 5
t SYNC 6
Output Clocks (Q0–Q10)
Test Conditions (Figure 3) 1
Min Typ Max Unit
Rise/fall time (0.8 V – 2.0V)
Figure 4
350
CLK ↑ to FBIN ↑ (TQ1089-MC500)
Figure 4
–850
CLK ↑ to FBIN ↑ (TQ1089-MC700)
Figure 4
–1050
Rise–rise, fall–fall (within group)
Figure 5
—
Rise–rise, fall–fall (group-to-group, aligned) Figure 6 (skew 2 takes into account skew 1) —
Rise-rise, fall-fall (group-to-group, non-aligned) Figure 7 (skew 3 takes into account skews 1, 2) —
Rise–fall, fall–rise
Figure 8 (skew 4 takes into account skew 3) —
Duty-cycle Variation
Figure 4
–1000
Period-to-Period Jitter
Figure 4
—
Random Jitter
Figure 4
—
Synchronization Time
—
—
–350
–350
60
75
—
—
0
80
190
10
1400
+150
+350
150
350
650
1200
+1000
200
400
500
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock.
tJP is the jitter on the output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1
R2
Z
+5 V
R1 Z
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
Y
FBIN Q0
Q1
Q2
•
•
•
•
CLK Q10
50 Ω
X
•
•
•
•
+5 V
R1 +5 V
R2 R1
R2
+5 V
R1
R2
For additional information and latest specifications, see our website: www.triquint.com
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TQ1089.PDF ] | |
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