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PDF TSEV83102G0BGL Data sheet ( Hoja de datos )
| Número de pieza | TSEV83102G0BGL | |
| Descripción | 10-bit 2 Gsps ADC | |
| Fabricantes | ATMEL Corporation | |
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Features
• Up to 2 Gsps Sampling Rate
• Power Consumption: 4.6 W
• 500 mVpp Differential 100 Ω or Single-ended 50 Ω (±2 %) Analog Inputs
• Differential 100 Ω or Single-ended 50 Ω Clock Inputs
• ECL or LVDS Output Compatibility
• 50 Ω Differential Outputs with Common Mode not Dependent on Temperature
• ADC Gain Adjust
• Sampling Delay Adjust
• Offset Control Capability
• Data Ready Output with Asynchronous Reset
• Out-of-range Output Bit
• Selectable Decimation by 32 Functions
• Gray or Binary Selectable Output Data; NRZ Output Mode
• Pattern Generator Output (for Acquisition System Monitoring)
• Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)
• CBGA 152 Cavity Down Hermetic Package
• CBGA Package Evaluation Board TSEV83102G0BGL
• Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0
Performance
• 3.3 GHz Full Power Input Bandwidth (-3 dB)
• Gain Flatness: ± 0.2 dB (from DC up to 1.5 GHz)
• Low Input VSWR: 1.2 Max from DC to 2.5 GHz
• SFDR = -59 dBc; 7.6 Effective Bits at FS = 1.4 Gsps, FIN = 700 MHz [-1 dBFS]
• SFDR = -53 dBc; 7.1 Effective Bits at Fs = 1.4 Gsps, FIN = 1950 MHz [-1 dBFS]
• SFDR = -54 dBc; 6.5 Effective Bits at FS = 2 Gsps, FIN = 2 GHz [-1 dBFS]
• Low Bit Error Rate (10-12) at 2 Gsps
Application
• Direct RF Down Conversion
• Wide Band Satellite Receiver
• High-speed Instrumentation
• High-speed Acquisition Systems
• High-energy Physics
• Automatic Test Equipment
• Radar
Screening
• Temperature Range for Packaged Device:
– “C” grade: 0° C < Tc; Tj < 90° C
– “V” grade: -20° C < Tc; Tj < 110° C
• Standard Die Flow (upon Request)
Description
The TS83102G0B is a monolithic 10-bit analog-to-digital converter, designed for digi-
tizing wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. It
uses an innovative architecture, including an on-chip Sample and Hold (S/H). The
3.3 GHz full power input bandwidth and band flatness performances enable the digitiz-
ing of high IF and large bandwidth signals.
10-bit 2 Gsps
ADC
TS83102G0B
2101D–BDC–06/04
1 page  
TS83102G0B
Electrical Operating Characteristics (Continued)
VCC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified VPLUSD range (from -0.9V to 1.7V);
VEE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Test
Level Symbol
Min
Typ
Max Unit
Analog input power level (50 Ω single-ended)
Analog input capacitance (die)
Input leakage current
Input resistance
- single-ended
- differential
Clock Inputs
4 PIN
4 CIN
4 IIN
4 RIN
4 RIN
49
98
- 2 dBm
0.3 pF
10 µA
50 51 Ω
100 102 Ω
Logic common mode compatibility for clock inputs
Differential ECL to LVDS
Clock inputs common voltage range (VCLK or VCLKB)
(DC coupled clock input)
AC coupled for LVDS compatibility (common mode
4
VCM
-1.2
0
0.3 V
1.2V)
Clock input power level (low-phase noise sinewave
input)
50 Ω single-ended or 100 Ω differential
Clock input swing (single ended; with CLKB = 50 Ω
to GND)
4
4
PCLK
VCLK
-4
±200
0
±320
4
±500
dBm
mV
Clock input swing (differential voltage) - on each
clock input
4
Clock input capacitance (die)
4
Clock input resistance
- single-ended
- differential ended
Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB, DRRB)
VCLK
VCLKB
CCLK
RCLK
RCLK
±141
45
90
±226
0.3
50
100
±354
55
110
mV
pF
Ω
Ω
- logic low
- logic high
Digital Inputs (DRRB Only)
4 VIL
VIH
-5
-2
-3 V
0V
Logic Compatibility
Negative ECL
- logic low
- logic high
4
VIL -1.810
VIH -1.165
-1.625
-0.880
V
V
2101D–BDC–06/04
5
5 Page 
TS83102G0B
Table 1. Explanation of Test Levels
Level
1
2
Explanation
100% production tested at 25°C (1) (for "C" temperature range) (2)
100% production tested at 25°C (1) and sample tested at specified temperatures (for "V" temperature ranges (2))
3 Sample tested only at specified temperatures
4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified
temperature)
5
6
Notes:
Parameter is a typical value guaranteed by design only
100% production tested over specified temperature range (for "B/Q" temperature range (2))
1. Unless otherwise specified
2. Refer to “Ordering Information” on page 55.
Only minimum and maximum values are guaranteed (typical values are issued from characterization results).
2101D–BDC–06/04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TSEV83102G0BGL.PDF ] | |
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