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PDF U6084B Data sheet ( Hoja de datos )

Número de pieza U6084B
Descripción PWM Power Control with Automatic Duty Cycle Reduction
Fabricantes TEMIC Semiconductors 
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U6084B
PWM Power Control with Automatic Duty Cycle Reduction
Description
The U6084B is a bipolar technology PWM-IC designed
for the control of an N-channel power MOSFET used as
a high-side switch. The IC is ideal for use in the brightness
control (dimming) of lamps such as, in dashboard
applications. For a constant brightness the preselected
duty cycle can be reduced automatically as a function of
the supply voltage.
Features
D Pulse width modulation up to 2 kHz clock frequency
D Protection against short circuit, load-dump
overvoltage and reverse VS
D Duty cycle 0 to 100 % continuously
D Output stage for power MOSFET
D Interference and damage protection according to
VDE 0839 and ISO/TR 7637/1.
D Charge pump noise suppressed
D Ground wire breakage protection
Ordering Information
Extended Type Number
U6084B–FP
Package
SO16
Remarks
Block Diagram
VS
16
9
Short circuit
latch monitoring
5
6
C1 47 kW
RC oscillator
Control input
3
C5
11
Current monitoring
+ short circuit detection
12
PWM
Logic
Charge 13
pump
14
Output
C2
Duty cycle
range
0–100%
Duty cycle
reduction
Voltage
monitoring
Enable/
disable
4 12
C6
95 9751
Rsh
VBatt
C3
47 nF
150W R3
Figure 1. Block diagram with external circuit
Ground
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
1 (8)

1 page




U6084B pdf
U6084B
Parameters
Test Conditions / Pins Symbol
Battery overvoltage detection
Pin 2
Stage 1:
– on
– off
VBatt
Stage 2:
– on
– off
VBatt
Stabilized voltage
Short-circuit protection
IS = 30 mA
Pin 16
Pin 12
VZ
Short-circuit current limita- VT1 = VS – V12
tion
VT1
Short-circuit detection
VT2 = VS – V12
VT2
VT1 – VT2
Delay timer short circuit detection
Pin 11
Switched off threshold
Charge current
Dicharge current
Capacitance current
Output short-circuit latch
Saturation voltage
Voltage doubler
VT11 = VS – V11
I5 = Ich – Idis
mI9 = 100 A
Pin 9
Pin 13
VT11
Ich
Idis
I5
Vsat
Voltage
Oscillator frequency
Internal voltage limitation
Gate output
Duty cycle 100%
I13 = 5 mA
(whichever is lower)
Pin 14
V13
f13
V13
V13
Voltage
Low level
WVBatt = 16.5 V,
Tamb = 110 °C, R3 = 150
High level,
duty cycle 100%
V14
V14
Current
V14 = Low level
V14 = High level, I13 > | I14 |
I14
Enable/ Disable
Pin 2
Current
Duty cycle reduction
Z-voltage
Oscillator
V2 = 0 V
mI4 = 500 A
Pin 4
I2
V4
Frequency
Threshold cycle
Upper
Lower
Oscillator current
Frequency tolerance
Pin6
+ a +V14
High, 1
VT100
VS
+ a +V14
Low, 2
tVT 100
VS
a + VTL
3 VS
VBatt = 12 V
C4 open, C2 = 470 nF,
duty cycle = 50%
f
a1
a2
a3
Iosc
f
Min.
18.3
16.7
25.5
19.5
18.5
85
75
3
9.5
13
2 VS
280
26
(VS+14)
0.35
1.0
–1.0
–20
6.9
10
0.68
0.65
0.26
26
6.0
*) Reference point is battery ground.
Typ.
20.0
18.5
28.5
23.0
20.0
100
90
10
9.8
23
3
20
150
400
27.5
(VS+15)
0.70
V13
–40
7.4
0.7
0.67
0.28
40
9.9
Max.
21.7
20.3
32.5
26.5
21.5
120
105
30
10.1
27
350
520
30.0
(VS+16)
0.95
1.5 *)
–60
8.0
2000
0.72
0.69
0.3
54
13.5
Unit
V
V
V
mV
mV
mV
V
mA
mA
mA
mV
kHz
V
V
mA
mA
V
Hz
mA
Hz
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
5 (8)

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