PDF TZA3015HW Data sheet ( Hoja de datos )

Número de pieza	TZA3015HW
Descripción	30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
Fabricantes	NXP Semiconductors
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INTEGRATED CIRCUITS DATA SHEET TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate™ 4-bit fibre optic transceiver Preliminary speciﬁcation Supersedes data of 2003 Oct 06 2003 Dec 16 1 page Philips Semiconductors 30 Mbit/s to 3.2 Gbit/s A-rate™ 4-bit ﬁbre optic transceiver Preliminary speciﬁcation TZA3015HW PINNING SYMBOL VEE VCCO VEE ENTXSC VCCD TXSD TXSDQ VCCD VCCD TXSC TXSCQ VCCD VEE UI RREF VCCA RXSD RXSDQ VCCA LOSTH RSSI LOS CS(DR0) SDA(DR1) SCL(DR2) VDD VEE LM0 LM1 LM2 INT ENRX ENTX VEE VCCO VEE PIN DESCRIPTION die common ground plane pad 1 supply voltage (clock generator) 2 ground 3 enable serial clock 4 digital supply voltage 5 serial data output 6 serial data output inverted 7 supply voltage (digital part) 8 supply voltage (digital part) 9 serial clock output 10 serial clock output inverted 11 supply voltage (digital part) 12 ground 13 user interface select input 14 reference resistor input 15 supply voltage (analog part) 16 serial data input 17 serial data input inverted 18 supply voltage (analog part) 19 loss of signal threshold input 20 received signal strength indicator output 21 loss of signal output 22 chip select output (data rate select input 0) 23 I2C-bus serial data input and output (data rate select input 1) 24 I2C-bus serial clock input (data rate select input 2) 25 supply voltage (digital) 26 ground 27 loop mode select input 0 28 loop mode select input 1 29 loop mode select input 2 30 interrupt output 31 enable receiver 32 enable transmitter 33 ground 34 supply voltage (clock generator) 35 ground SYMBOL VCCD WINSIZE INWINDOW VCCD VEE LOWSWING FREF0 ENBA VCCD ENDDR RXFP RXFPQ RXPAR RXPARQ VEE VCCD RXPC RXPCQ VCCD RXPD0 RXPD0Q RXPD1 RXPD1Q RXPD2 RXPD2Q RXPD3 RXPD3Q VCCD TXPC TXPCQ VCCD TXPD0 TXPD0Q TXPD1 TXPD1Q TXPD2 TXPD2Q TXPD3 TXPD3Q PIN DESCRIPTION 36 supply voltage (digital part) 37 wide and narrow frequency detect window select input 38 frequency window detector output 39 supply voltage (digital part) 40 ground 41 enable low LVDS swing 42 reference frequency select input 0 43 enable byte alignment 44 supply voltage (digital part) 45 enable DDR 46 frame pulse output 47 frame pulse output inverted 48 parity output 49 parity output inverted 50 ground 51 supply voltage (digital part) 52 parallel clock output 53 parallel clock output inverted 54 digital supply voltage 55 parallel data output 0 56 parallel data output 0 inverted 57 parallel data output 1 58 parallel data output 1 inverted 59 parallel data output 2 60 parallel data output 2 inverted 61 parallel data output 3 62 parallel data output 3 inverted 63 supply voltage (digital part) 64 parallel clock input 65 parallel clock input inverted 66 supply voltage (digital part) 67 parallel data input 0 68 parallel data input 0 inverted 69 parallel data input 1 70 parallel data input 1 inverted 71 parallel data input 2 72 parallel data input 2 inverted 73 parallel data input 3 74 parallel data input 3 inverted 2003 Dec 16 5 5 Page Philips Semiconductors 30 Mbit/s to 3.2 Gbit/s A-rate™ 4-bit ﬁbre optic transceiver Preliminary speciﬁcation TZA3015HW DATA AND CLOCK RECOVERY (DCR) The TZA3015HW recovers the clock and data contents from the incoming bit stream; see Fig.6. The DCR uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition on any bit rate between 30 Mbit/s and 3.2 Gbit/s. At power-up, coarse adjustment of the free running Voltage Controlled Oscillator (VCO) frequency is required. This is achieved by the Frequency Window Detector (FWD) circuit. The FWD is a conventional frequency locked PLL. The FWD checks the VCO frequency, which has to be within a 1000 ppm window around the required frequency. The FWD then compares the divided VCO frequency, also available on pins RXPRSCL(Q), with the reference frequency on pins CREF(Q), usually 19.44 MHz. If the VCO frequency is outside this window, the FWD disables the Data Phase Detector (DPD) and forces the VCO to a frequency within the window. As soon as the ‘in window’ condition occurs, which is visible on pin INWINDOW, the DPD is enabled and will lock on the incoming bit stream. Since the VCO frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. Although the VCO is now locked to the incoming bit stream, the FWD is still supervising the VCO frequency and takes over control if the VCO frequency drifts outside the predefined frequency window. This might occur during a ‘loss of signal’ situation. Due to the FWD, the VCO frequency is always close to the required bit rate, enabling rapid phase acquisition when the lost input signal returns. Due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. Any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. This only holds if the TZA3015HW is used as a receiver since the synthesizer of the transmitter uses the same reference clock. The transmitter does need a very accurate reference frequency. Fractional N synthesizer in the DCR The DCR section contains a fractional N synthesizer as frequency acquisition aid for the A-rate functionality. This allows the DCR to synchronize on incoming data, regardless of the received bit rate. Any combination of bit rate and reference frequency is possible, due to the 22 bits fractional N synthesizer, allowing approximately 10 Hz frequency resolution. The LSB (bit K0) should be set to logic 1 to avoid limit cycles (cycles of less than maximum length). This leaves 21 bits (bits K[21:1]), available for free programming. handbook, full pagewidth from limiting amplifier and DLB MUX OCTAVE DIVIDER ÷M divided CREF(Q) MAIN Frac DIVIDER N, K ÷N REFERENCE DIVIDER DATA PHASE DETECTOR recovered data recovered clock up down CHARGE PUMP to demultiplexer VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER + FREQUENCY WINDOW DETECTOR up down CHARGE PUMP PRESCALER BUFFER INWINDOW WINSIZE Fig.6 Functional diagram of data and clock recovery. RXPRSCL(Q) MGU683 2003 Dec 16 11 11 Page

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