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TZA3001 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer TZA3001
Beschreibung SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
TZA3001 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
TZA3005H
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
Product specification
Supersedes data of 1997 Aug 05
File under Integrated Circuits, IC19
2000 Feb 17






TZA3001 Datasheet, Funktion
Philips Semiconductors
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
Product specification
TZA3005H
handbook, full pagewidth
VCC(SYNOUT) 1
GNDSYNOUT 2
REFSEL0 3
REFSEL1 4
DGNDSYN 5
VCCD(SYN) 6
VCCA(SYN) 7
AGNDSYN 8
AGNDSYN 9
TEST1 10
TEST2 11
GND 12
TEST3 13
REFCLKQ 14
REFCLK 15
VCC(TXOUT) 16
TZA3005H
48 MRST
47 RXPCLK
46 VCC(RXOUT)
45 RXPD7
44 RXPD6
43 RXPD5
42 GNDRXOUT
41 RXPD4
40 RXPD3
39 RXPD2
38 VCC(RXOUT)
37 RXPD1
36 RXPD0
35 FP
34 GNDRXOUT
33 OOF
MGK483
2000 Feb 17
Fig.2 Pin configuration.
6

6 Page









TZA3001 pdf, datenblatt
Philips Semiconductors
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
Product specification
TZA3005H
Table 6 Truth table operating modes
ALTPIN TEST1 TEST2 TEST3 BUSWIDTH MODE
(pin 50) (pin 10) (pin 11) (pin 13) (pin 30) (pin 49)
SD(1)
0 XX0 X
0X
0 XX0 0
10
0 XX0 0
0 XX0 1
0 XX1 X
1000X
1001X
1010X
1010X
XXXXX
XXXXX
11
1X
XX
XX
XX
X0
X1
XX
XX
LLEN DLEN
FUNCTIONAL
(pin 31) (pin 32) OPERATING MODE
1 1 normal operation
(STM1 byte/nibble)
1 1 squelched clock
operation
(STM4 byte)
1 1 normal operation
(STM4 byte)
1 1 normal operation
(STM4 byte)
1 1 loop timing
1 1 normal operation
1 1 loop timing
1 1 squelched clock
operation
1 1 normal operation
X 0 diagnostic loopback
0 X line loopback
Note
1. SD denotes either pin 22 (SDTTL) or pin 23 (SDPECL) (signal present = active = 1; loss of signal = inactive = 0).
During a loss of signal, the outputs RXPD0 to RXPD7 are forced to zero (see Table 5).
Receiver frame alignment
Figure 3 shows a typical frame and boundary alignment
sequence. Frame and byte boundary detection is enabled
on the rising edge of OOF and remains enabled while OOF
is HIGH. Byte boundaries are recognized after the third A2
byte is received. FP goes HIGH for one RXPCLK cycle to
indicate that this is the first data byte with the correct byte
alignment on the output parallel data bus
(RXPD0 to RXPD7).
When interfaced with a section terminating device, OOF
must remain HIGH for a full frame period after the initial
frame pulse (FP). This is to allow the section terminating
device to internally verify that frame and byte alignment
are correct (see Fig.4). Because at least one frame pattern
will have been detected since the rising edge of OOF,
boundary detection is disabled when OOF goes LOW.
The frame and byte boundary detection block is activated
on the rising edge of OOF, and remains active until a frame
pulse (FP) occurs and OOF goes LOW, whichever occurs
last. Figure 4 shows a typical OOF timing pattern when the
TZA3005H is connected to a down stream section
terminating device. OOF stays HIGH for one full frame
after the first frame pulse (FP). The frame and byte
boundary detection block is active until OOF goes LOW.
Figure 5 shows frame and byte boundary detection
activated on the rising edge of OOF, and deactivated by
the first frame pulse (FP) after OOF goes LOW.
2000 Feb 17
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