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PDF TZA1032UK Data sheet ( Hoja de datos )
| Número de pieza | TZA1032UK | |
| Descripción | Laser driver and controller circuit | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TZA1032
Laser driver and controller circuit
Preliminary specification
2002 May 06
1 page  
Philips Semiconductors
Laser driver and controller circuit
Preliminary specification
TZA1032
4 QUICK REFERENCE DATA
SYMBOL
VDD[1 to 3]
IOUT[1 to 3]
ROUT[1 to 3]
tr, tf
rlmin
BLPC(−3dB)
Balpha(−3dB)
fmod
tW(min)
tres
PARAMETER
CONDITION
output supply voltage
output current (threshold)
output current (delta)
output resistance
rise and fall time
depends on package
and load
decodable run length
−3dB LPC bandwidth
−3dB alpha bandwidth
modulator frequency
PLL locked to
external clock
PLL in Current
Controlled Oscillator
(CCO) mode
minimum pulse width
timing resolution
MIN.
3.0
1
0
−
−
1
−
−
250
240
4
2
TYP.
3.3
−
−
120
−
−
1
50
−
−
−
−
MAX.
3.6
200
240
−
1 to 2
UNIT
V
mA
mA
Ω
ns
15
− kHz
− kHz
565 MHz
440 MHz
− ns
− ns
2002 May 06
5
5 Page 
Philips Semiconductors
Laser driver and controller circuit
Preliminary specification
TZA1032
7 FUNCTIONAL DESCRIPTION
7.1 The I2C-bus interface
The TZA1032 has two possible I2C-bus addresses that can be selected via pin I2C_A0, an active HIGH digital CMOS
input. This allows two TZA1032 ICs to be independently applied using the same I2C-bus (e.g. for double write
applications), one with pin I2C_A0 HIGH and the other with pin I2C_A0 LOW. The TZA1032 operates as a slave only
I2C-bus device.
Table 1 TZA1032 I2C-bus addresses
I2C_A0
I2C-BUS WRITE ADDRESS
0 = LOW
1 = HIGH
1101 1100 (DCH)
1101 1110 (DEH)
I2C-BUS READ ADDRESS
1101 1101 (DDH)
1101 1111 (DFH)
Each I2C-bus register has an 8-bit register address bus. The various modes in which an external controller can use the
I2C-bus interface are shown in Table 2. The special RAM Write mode allows fast block transfer of data via one single
I2C-bus register address.
Table 2 I2C-bus communication modes supported by TZA1032
I2C-BUS MODE
I2C-BUS INFORMATION
Write
Incremental write
RAM write
Read
Successive read
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge;
data_to_register_address (n); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge;
data_to_register_address (n); acknowledge; data_to_register_address (n + 1);
acknowledge; .... ; data_to_register_address (n + r); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (= RAM x), acknowledge;
data_to_RAM x (0), acknowledge; data_to_RAM x (1), acknowledge; .... ;
data_to_RAM x (m); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge; stop
start; TZA1032_read_address; acknowledge; data_from_register_address (n);
acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge; start;
TZA1032_read_address; acknowledge; data_from_register_address (n), acknowledge;
data_from_register_address (n); acknowledge; .... ; data_from_register_address (n);
acknowledge; stop
7.2 Interrupt request
The IRQ is built as an active LOW open-drain output pin so it can be linked to the system controller together with similar
signals in a wired-or approach. An IRQ register is present to select the conditions which can cause the IRQ line to be
active. Possible conditions for an interrupt can be overrun or under-run of threshold or delta laser current or several other
selectable conditions.
The status register allows extra signals to be monitored in non-interrupt mode (e.g. by polling). The IRQ and status
registers in combination with the IRQ line allow a very efficient way of controlling TZA1032.
In addition, the IRQ_enable register allows selectable masking of most of the IRQ conditions to the IRQ line.
2002 May 06
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TZA1032UK.PDF ] | |
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