Datenblatt-pdf.com


TZA1032 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer TZA1032
Beschreibung Laser driver and controller circuit
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 24 Seiten
TZA1032 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
TZA1032
Laser driver and controller circuit
Preliminary specification
2002 May 06






TZA1032 Datasheet, Funktion
Philips Semiconductors
Laser driver and controller circuit
Preliminary specification
TZA1032
5 BLOCK DIAGRAM
handbook, full pagewidth
TZA1032UK
DATAP
DATAN
CLKP
CLKN
25 Data
26
RLC
DIFFERENTIAL
24 RECEIVER Clk
23
SAMPLE
TIMING
GENERATOR
43
44
42
RLC
DECODER
threshold
RLC to WS
& SETPOINT
POWER
CONVERTER
delta
(8 bits)
MULTIPLYING
CURRENT
DACs
1, 2, 49
3
50, 51,
52
3
4
ES
ES
RDWR
VDD
OUT[1 to 3]
VSS
REFH
REFL
31
ANALOG
32 REFERENCE
PLL
LCA clock
LCD clock
45
FS
FS_ADC
P_readSet
CFS
33
LASER
CONTROL
ANALOG
LASER
CONTROL
DIGITAL
P_writeSet
threshold (16 bits)
delta (8 bits)
AMEAS
LASP
AEZ
34
35
37
Alpha_ADC
LasP_DAC
LPC LOOP;
ALPHA LOOP
AND OPC
RDWR
OPC
15
SCL
SDA
IRQ
I2C_A0
40
41
14
16
I2C-BUS
INTERFACE
to all blocks
POWER-ON
RESET
Supply
ANALOG
POWER
DIGITAL
POWER
20
n.c.
REFERENCE
DACs
5, 6, 7
3 9, 10
2 13
TEST
INTERFACE
2
11, 12
36
39
29
28
TEST[2 to 0]
TEST_IN[1 to 0]
TEST_CLK
TEST_OUT[1 to 0]
FSPLUS
FSMIN
IVREFCON
IVCON
33
22, 27, 19, 30,
46 48
43
8, 17, 3, 18,
21, 38 47
VDDA VSSA
VDDD VSSD
Fig.1 Block diagram.
MGW501
2002 May 06
6

6 Page









TZA1032 pdf, datenblatt
Philips Semiconductors
Laser driver and controller circuit
Preliminary specification
TZA1032
7.3 Soft reset and power-down
TZA1032 has a soft reset register that can reset most of
the internal blocks, and is automatically synchronized with
the I2C-bus SCL input.
Most of the blocks in the TZA1032 are provided with a
power-down input. The IC features a special power-down
register which can be programmed via I2C-bus. An active
bit in the register causes a block to go into a low dissipation
standby mode. This offers the user the possibility to save
power when TZA1032 operates in a register mode (e.g.
during read).
7.4 The Phase Locked Loop
The PLL is phase locked to the incoming RLC clock signal.
A single external clock signal is sufficient for a complete
task of TZA1032. The PLL unit provides all internal
clocking with the exception of the I2C-bus interface that
can run on its own SCL clock.
The PLL can be used in closed loop or as a stable
open-loop oscillator (in read mode for example) when no
input clock is present. For this purpose the PLL features a
self-learning oscillator mode for non-locked operation.
Furthermore, the PLL is designed for wide range
frequency locking (factor 2.5). The frequency
multiplication factor is programmable for flexible selection
of write strategy timing resolution for different standards
(CD 1× to 24×, DVD 1×, 2×, 4× and DVR).
For PLL characteristics see Table 3 for the possible PLL
frequencies and write strategy resolutions with respect to
the incoming RLC clock. The TZA1032 features are much
more flexible than shown in Table 3. The PLL frequency
and write strategy resolution can be programmed
according to the specific requirements of the user.
Table 3 Examples of PLL clock ratio programming
STANDARD
CD × 1
CD × 2
CD × 4
CD × 8
CD × 12
CD × 16
CD × 24
DVD × 1
DVD × 2
DVD × 2.5
DVD × 4
DVR-1
DVR-2
RLC FREQUENCY
frlc (MHz)
4.3218
8.6436
17.2872
34.5744
51.8616
69.1488
103.7232
26.16
52.32
65.4
104.64
65.625
93.75
PLL FREQUENCY
fo (MHz)
518.616
518.616
553.1904
553.1904
414.8928
553.1904
414.8928
523.2
523.2
392.4
418.56
525
562.5
Note
1. The write strategy resolution is defined as the number of bits per RLC clock period.
WRITE STRATEGY
RESOLUTION(1)
8
8
8
8
8
8
4
20
10
6
4
8
6
7.5 The differential receiver
A differential RLC receiver (DRX) with low voltage-swing is present to allow high data rates in combination with low
electromagnetic interference. The receiver features impedance matching with typical flex foils. Furthermore, single side
operation is optionally possible by connecting additional external resistors.
High-impedance input switching allows two or more TZA1032 ICs to operate in parallel. The high-impedance input switch
is controlled by a single I2C-bus control register that can individually select DRX clock and/or data lines for
high-impedance mode. A high-impedance input mode is also entered during Reset or power-down.
2002 May 06
12

12 Page





SeitenGesamt 24 Seiten
PDF Download[ TZA1032 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
TZA1032Laser driver and controller circuitNXP Semiconductors
NXP Semiconductors
TZA1032UKLaser driver and controller circuitNXP Semiconductors
NXP Semiconductors
TZA1035HLHigh speed advanced analog DVD signal processor and laser supplyNXP Semiconductors
NXP Semiconductors
TZA1038HWHigh speed advanced analog DVD signal processor and laser supplyNXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche