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US1050CM Schematic ( PDF Datasheet ) - UNISEM

Teilenummer US1050CM
Beschreibung 5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR
Hersteller UNISEM
Logo UNISEM Logo 




Gesamt 7 Seiten
US1050CM Datasheet, Funktion
FEATURES
Guaranteed < 1.3V Dropout at Full Load
Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-in Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as :
P54C,P55C,Cyrix M2,
POWER PC,AMD
GTL+ Termination
PENTIUM PRO, KLAMATH
Low Voltage Memory Termination Applications
Standard 3.3V Chip-Set and Logic Applications
US1050
5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
DESCRIPTION
The US1050 product is a low dropout three terminal ad-
justable regulator with minimum of 5A output current
capability. This product is specifically designed to pro-
vide well regulated supply for low voltage IC applications
such as PentiumP54C,P55Cas well as GTL+
termination for Pentium Proand Klamathpro-
cessor applications . The US1050 is also well suited for
other processors such as Cyrix,AMD and Power
PCapplications. The US 1050 is guaranteed to have
<1.3V drop out at full load current making it ideal to
provide well regulated outputs of 2.5V to 3.6V with 4.75V
to 7V input supply.
TYPICAL APPLICATION
5V
C1
1500uF
Vin 3
US1050 Vout 2
Adj 1
3.38V / 5A
R1
121
C2
R2 2x 1500uF
205
1050app1-1.1
Typical Application of US1050 in a 5V to 3.38V regulator designed
to meet the Intel P54C Processors.
Notes: Pentium P54C,P55C ,Klamath,Pentium Pro,VRE,are trade marks of Intel Corp.Cyrix M2 is trade mark of Cyrix Corp.
Power PC is trade mark of IBM Corp.
PACKAGE ORDER INFORMATION
Tj (°C)
0 TO 150
3 PIN PLASTIC
TO220 (T)
US1050CT
3 PIN PLASTIC
TO263 (M)
US1050CM
2 PIN PLASTIC
POWER FLEX (P)
US1050CP
3 PIN PLASTIC
TO252 (D)
US1050CD
Rev. 1.3
10/27/00
2-33






US1050CM Datasheet, Funktion
US1050
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equalto the (VESR=ESR*I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (VESL
=L*I/t) . The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current ,
(VC = t * I / C ) where t is the response time of the
regulator.
ESR 37 =8 m
4.6
The Sanyo MVGX series is a good choice to achieve
both price and performance goals.The 6MV1500GX ,
1500uF, 6.3V has an ESR of less than 36 mtyp .
Selecting 5 of these capacitors in parallel has an ESR
of 7.2 mwhich achieves our design goal.
The next step is to calculate the drop due to the capaci-
tance discharge and make sure that this drop in voltage
is less than the selected ESL drop in the previous step.
V ESR
V ESL
LOAD
CURRENT
T
VC
1050plt1-1.0
2) The output capacitance is 5X1500 uF = 7500uF
VC = t × ∆I = 2×4.6 =1.2 mV
C 7500
Where :
t=2 uS is the regulator response time
LOAD CURRENT RISE TIME
To set the output DC voltage, we need to select R1 and
R2 :
Figure 4 - Typical Regulator response to the fast load
current step.
An example of a regulator design to meet the Intel
P54CVRE specification is given below .
3) Assuming R1=121 , 0.1%
R2=

VOUT
VREF
1
×121=

3.5
1.25
1
×121=217.8
Select R2=218 ,0.1%
Assume the specification for the processor as shown in
Table 1:
Type of
Processor
Intel-P54C VRE
Vout
Nominal
3.50 V
Imax
4.6 A
Max Allowed
Output Tolerance
±100 mV
Selecting both R1 and R2 resistors to be 0.1% toler-
ance, results in the least amount of error introduced by
the resistor dividers leaving ≈ ±1.3% error budget for
the US1050 reference which is within the initial accu-
racy of the device.
Table 1 - Processr Specification
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR :
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is ≈ ±53 mV (±1.5% of 3.5V nomi-
nal) ,then the total step allowed for the ESR and the
ESL, is 47 mV .
Assuming that the ESL drop is 10mV ,the remaining
ESR step will be 37 mV . Therefore the output capaci-
tor ESR must be :
Finally , the input capacitor is selected as follows :
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the main
power supply response time is 50 uSec, then the mini-
mum input capacitance for a 4.6A load step is given by
CIN = 4.6×50 =1530 µF
0.15
2-38
Rev. 1.3
10/27/00

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