Datenblatt-pdf.com


VG36648041BT-10 Schematic ( PDF Datasheet ) - Vanguard International Semiconductor

Teilenummer VG36648041BT-10
Beschreibung CMOS Synchronous Dynamic RAM
Hersteller Vanguard International Semiconductor
Logo Vanguard International Semiconductor Logo 




Gesamt 30 Seiten
VG36648041BT-10 Datasheet, Funktion
VIS
Description
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7/8ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X8 organization
• Input/Output controlled by DQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0153
Rev.1
Page 1






VG36648041BT-10 Datasheet, Funktion
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C V DD = 3.3V ± 0.3VSS = 0V)
Test Conditions for LVTTL Compatible :
AC input Levels (VIH/VIL)
Input rise and fall time
2.0/0.8V
1ns
Input timing reference level/
Output timing reference level
Output load condition
1.4V
50pF
AC Test Load Circuits (for LVTTL interface) :
VDDQ
VOUT
Device
Under
Test
VDDQ
Z = 50
50PF
Document : 1G5-0153
Rev.1
Page 6

6 Page









VG36648041BT-10 pdf, datenblatt
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Current
CS RAS CAS WE Address
Command
Action
(3/3)
Notes
Write
H X X XX
recovering L H H H X
DESL
NOP
Nop Enter row active after tDPL
Nop Enter row active after tDPL
L H H LX
BST
Nop Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Start read, Determine AP
8
L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
ILLEGAL
3
L L L HX
PEF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
Write
H X X XX
recovering
with auto
L
H
H HX
precharge L H H L X
DESL
NOP
BST
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL
3,8,11
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
3,11
L L H H BA, RA
ACT
ILLEGAL
3,11
L L H L BA, A10
PRE/PALL
ILLEGAL
3
L L L HX
REF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
Auto
H X X XX
Refreshing
L
H
H XX
L H L XX
DESL
NOP/BST
READ/WRIT
Nop Enter idle after tRC
Nop Enter idle after tRC
ILLEGAL
L L H XX
ACT/PRE/PALL ILLEGAL
L L L XX
Mode regis- H X X X X
ter
setting
L H H HX
L H H LX
REF/SELF/MRS ILLEGAL
DESL
Nop Enter idle after 2 Clocks
NOP
Nop Enter idle after 2 Clocks
BST
ILLEGAL
L H L XX
READ/WRITE ILLEGAL
L L X XX
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which dont’ satisfy t DPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Document : 1G5-0153
Rev.1
Page 12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ VG36648041BT-10 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
VG36648041BT-10CMOS Synchronous Dynamic RAMVanguard International Semiconductor
Vanguard International Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche