|
|
PDF VG3617801CT Data sheet ( Hoja de datos )
| Número de pieza | VG3617801CT | |
| Descripción | 16Mb CMOS Synchronous Dynamic RAM | |
| Fabricantes | Vanguard International Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de VG3617801CT (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Description
The VG3617801CT is CMOS Synchronous Dynamic RAMs organized as 1,048,576-word X 8-bit X 2-
bank. It is fabricated with an advanced submicron CMOS technology and is designed to operate from a sin-
gle 3.3V power supply. This is packaged using JEDEC standard pinouts and standard plastic TSOP.
Features
• Single 3.3V(±0.3V ) power supply
• Clock Frequency:100MHz
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual Internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X8 organization
• Input/output control by DQM
• 2048 refresh cycles/32ms
• Burst termination by burst stop and precharge command
• Burst read single write option
Document:1G5-0133
Rev.1
Page 1
1 page  
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
DC Characteristics(Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Test Conditions
ICC1 Burst length=1
CL=3
-8H
Min Max
90
VG3617801CT
-8L -10
Min Max Min Max
90 85
Unit
mA
tRC ≥ tRC (MIN.),Io=0mA CL=2
One bank active
Precharge standby
current in power
down mode
ICC2P CKE ≤ V IL(MAX.)tCK=15ns
ICC2PS CKE ≤ V IL(MAX)tCK= ∞
Precharge standby
current in Nonpower
down mode
ICC2N
CKE ≥ V IH(MIN.)tCK=15ns
CS ≥ V IH(MIN.)
Input signals are changed.
one time during 30ns.
ICC2NS CKE ≥ V IH(MIN.), tCK= ∞
CLK ≤ V IL(MAX.)
Input signals are stable.
Active standby current Icc3P
in power down mode
Icc3PS
CKE ≤ V IL(MAX.),tCK=15ns
CKE ≤ V IL(MAX.),tCK= ∞
Active standby current Icc3N
in nonpower down
mode
CKE ≥ V IL(MAX.),tCK=15ns
CS ≥ V IL(MIN.)
Input signals are changed
one time during 30ns
Icc3NS
CKE ≥ V IH(MIN.) tCK= ∞
CLE ≤ V IL(MAX.)
Input signals are stable.
Operating current
(Burst mode)
Icc4 tCK ≥ tCK (MIN.),Io=0mA CL=3
Burst length=4
CL=2
85 85
33
22
30 30
80
3
2
30
66
33
22
30 30
6
3
2
30
15 15
15
120 120
115 105
105
100
Refresh current
Icc5
Self refresh current Icc6
Input leakage current ILI
Output leakage current ILO
Output Low Voltage VOL
Output High Voltage VOH
tRC ≥ tRC (MIN.)
CL=3
CL=2
110 110
105 105
100
95
CKE ≤ 0.2V
22
2
Vin ≥ 0 , Vin ≤ VDD +0.3V
-5 5 -5 5 -5 5
Pins not under test=0V
VOUT ≥ 0 , VOUT ≤ VDD +0.3V -5 5 -5 5 -5 5
DQ# in H-Z., Dout disabled
IOL=2mA
0.4 0.4
0.4
IOH=2mA
2.4 2.4 2.4
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
Notes
1,2
1,2
2
Notes 1.Icc depends on output loading and cycle rates. Specified values are obtained with the output open.
2.Icc is measured on condition that addresses are changed only one time during tCK(MIN.).
Document:1G5-0133
Rev.1
Page 5
5 Page 
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Current state
Write
recovering
Write
recovering
with auto
precharge
Refreshing
Mode register
accessing
CS RAS CA WE Address
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-Code
H X X XX
L H H XX
L H L XX
L L H XX
L L L XX
H X X XX
L H H HX
L H H LX
L H L XX
L L X XX
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
REF/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL/
REF/SELF/MRS
Action
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after 2 Clocks
Nop → Enter idle after 2 Clocks
ILLEGAL
ILLEGAL
ILLEGAL
(3/3)
Notes
8
3
3
3,8
3
3
3
Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. IIIegal if tRCD is not satisfied.
6. IIIegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data if tDPL is not satisfied.
10. IIIegal if tRRD is not satisfied.
Document:1G5-0133
Rev.1
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VG3617801CT.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| VG3617801CT | 16Mb CMOS Synchronous Dynamic RAM | Vanguard International Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |