PDF VG3617161ET Data sheet ( Hoja de datos )

Número de pieza	VG3617161ET
Descripción	CMOS Synchronous Dynamic RAM
Fabricantes	Vanguard International Semiconductor
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No Preview Available ! VIS VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM Description The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed applica- tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II. Features • Single 3.3V +/- 0.3V power supply • Clock frequency:166MHz, 143MHz, 125MHz • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (Sequential/Interleave) • Automatic precharge and controlled precharge • Auto refresh and self refresh modes • Dual internal banks controlled by A11(Bank select) • Simultaneous and independent two bank operation • I/O level : LVTTL interface • Random column access in every cycle • X16 organization • Byte control by LDQM and UDQM • 4096 refresh cycles/64ms • Burst termination by burst stop and precharge command Document:1G5-0189 Rev.1 Page 1 1 page VIS VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM IDD Specifications (VDD = 3.3V ± 0.3V, TA = 0 ~ 70°C) Description/test condition Operating Current tRC ≥ tRC(min), outputs open Address changed once during tCK(min). Burst length = 1 (One bank active) Precharge Standby Current in non power-down mode CKE ≥ VIH (min), CS ≥ VIH (min), tCK =tCK(min) Input signals are changed once during 2 clocks Precharge Standby Current in non power-down mode CKE ≥ VIH (min), tCK = ∞ , CLK ≤ VIL (max) Input signals are stable Precharge Standby Current in power-down mode CKE ≤ VIL (max), tCK = tCK(min) Symbol IDD1 IDD2N IDD2NS IDD2P -6 Min Max 115 40 35 2 Precharge Standby Current in power-down mode CKE ≤ VIL (max), tCK = ∞ , CLK ≤ VIL (max) IDD2PS 2 Active Standby Current in non power-down mode CKE ≥ VIH (min), CS ≥ VIH(min), tCK = tCK(min) Input signals are changed once during 2 clocks Active Standby Current in non power-down mode CKE ≥ VIH (min), tCK = ∞ , CLK ≤ VIL (max) Input signals are stable Active Standby Current in power-down mode ≤CKE VIL (max), tCK = tCK(min) Active Standby Current in power-down mode CKE ≤ VIL (max), tCK = ∞ , CLK ≤ VIL (max) IDD3N IDD3NS IDD3P IDD3PS 50 40 35 35 Operating Current (Page burst, and all banks activated) tCCD = tCCD(min), outputs open, gapless data Refresh Current tRC ≥ tRC (min) (tREF = 64ms) Self Refresh Current CKE ≤ 0.2V IDD4 IDD5 IDD6 150 100 1 -7 Min Max 105 40 35 2 2 50 40 35 35 140 90 1 -8 Min Max 95 Unit Note 3,4 40 3 35 mA 2 2 50 3 40 35 35 130 4,5 80 3 1 Document:1G5-0189 Rev.1 Page 5 5 Page VIS VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM (2/3) Current state Read with auto precharge Write with auto precharge Precharging Row activating CS RAS CA WE Address H X X XX L H H HX L H H LX L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L H L BA,A10 L L L HX L L L L Op-Code H X X XX L H H HX L H H LX L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L H L BA,A10 L L L HX L L L L Op-code H X X XX L H H HX L H H LX L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L H L BA,A10 L L L HX L L L L Op-Code H X X XX L H H HX L H H LX L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L H L BA,A10 L L L HX L L L L Op-Code Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Continue burst to end → Prech arging Continue burst to end → Prech arging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end → Write recovering with auto precharge Continue burst to end → Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter row active after tRCD Nop → Enter row active after tRCD Nop → Enter row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 3 3 3 3 3 3 3 3 3 3,10 3 Document:1G5-0189 Rev.1 Page 11 11 Page

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