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Teilenummer | VG3617161DT |
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Beschreibung | 16Mb CMOS Synchronous Dynamic RAM | |
Hersteller | Vanguard International Semiconductor | |
Logo | ||
Gesamt 30 Seiten VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Description
The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
• Single 3.3V +/- 0.3V power supply
• Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X16 organization
• Byte control by LDQM and UDQM
• 4096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
Document:1G5-0160
Rev.1
Page 1
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
A.C Characteristics:
Test Conditions: (Ta=0 to 70°C V DD=3.3V ±0.3V ,VSS=0V)
symbol
A.C. Parameter
-5.5 -6 -7 -8
Min. Max. Min. Max. Min. Max. Min. Max. unit note
tCH Clock high time
2 2 2.5 3 ns
tCL Clock low time
2 2 2.5 3
tT Transition time (Rise and Fall)
0.5 10 0.5 10 0.5 10 0.5 10
tCK3 Clock cycle time
CL* = 3 5.5
6
7
8
tCK2
CL* = 2
8
8.5 10
12
tIS Data/Address/Control Input setup time 2
222
tIH
Data/Address/Control Input hold time
1
111
tLZ Data output low impedance 1 1 1 1
tHZ3 Data output high impedance CL* = 3 4.5 5 5 7
tHZ2
CL* = 2
6 6.5 7
89
tAC3 Access time from CLK CL* = 3
(positive edge)
tAC2
CL* = 2
5 5.5 6
7 77
7
8
tOH Data output hold time
2.2 2.5 2.5 2.5
tRCD
RAS to CAS delay
16.5 18 20 20
tRRD
Row activate to row activate delay
11
12 14 16
tCCD
CAS to CAS Delay time
1 1 1 1 CLK
tWR Write recovery time
1tCK
+2ns
1tCK
+2ns
1
1 CLK
tRAS
Row activate to precharge time
33 100,000 36 100,000 40 100,000 48 100,000 ns
tRP Precharge to refresh/row activate
16.5
18
20
command
20 ns
tDAL3
Data-in to ACT (REF) Command (CL = 2clk+
3) tRP
2clk+
tRP
2clk+
tRP
2clk+
tRP
tDAL2
Data-in to ACT (REF) Command (CL = 1clk+t
2) RP
1clk+
tRP
1clk+
tRP
1clk+
tRP
tRC Row cycle time
55 54 62 72 ns
tRSC
(Special) Mode Register Set Cycle time 2
2 2 2 CLK
tREF
Refresh time
64 64 64 64 ms
tSRX
Minimum CKE ”High”for Self-Refresh
exit
1
1 1 1 CLK
tBDL Last data in to burst STOP command 1
1 1 1 CLK
tPDE
Power Down Exit set-up time
5
5 5 6 ns
Document:1G5-0160
Rev.1
Page 6
6 Page VIS
Current state
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
CS RAS CA WE Address
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-code
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-Code
H X X XX
L H H HX
L H H LX
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
L L L L Op-Code
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
(2/3)
Action
Continue burst to end → Prech arging
Continue burst to end → Prech arging
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue burst to end → Write
recovering with auto precharge
Continue burst to end → Write
recovering with auto precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
Nop → Enter row active after tRCD
Nop → Enter row active after tRCD
Nop → Enter row active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
3
3
3
3
3
3
3
3
3
3,10
3
Document:1G5-0160
Rev.1
Page 12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ VG3617161DT Schematic.PDF ] |
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