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PDF VG36128161BT Data sheet ( Hoja de datos )
| Número de pieza | VG36128161BT | |
| Descripción | CMOS Synchronous Dynamic RAM | |
| Fabricantes | Vanguard International Semiconductor | |
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VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Description
The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchro-
nous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x
16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
.
Document :1G5-0183
Rev.1
Page 1
1 page  
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Value
Unit
Supply Voltage
VDD with respect to VSS
-0.5 to 4.6
V
Supply Voltage for Output
VDDQ
with respect to VSSQ
-0.5 to 4.6
V
Input Voltage
VI with respect to VSS
-0.5 to 4.6
V
Output Voltage
VO with respect to VSSQ
-0.5 to 4.6
V
Short circuit output current
IO
50 mA
Power dissipation
PD Ta = 25 °C
1W
Operating temperature
TOPT
0 to 70
°C
Storage temperature
TSTG
-65 to 150
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational section of this
specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (Ta = 0 ~ 70 °C, unless otherwise noted)
Parameter
Symbol
Min.
Limits
Typ.
Supply Voltage
VDD
3.0
3.3
Supply Voltage for DQ
VDDQ
3.0
3.3
Ground
VSS
0
0
Ground for DQ
VSSQ
0
0
High Level Input Voltage (all inputs)
VIH
2.0
Low Level Input Voltage (all inputs)
VIL
-0.3
Max.
3.6
3.6
0
0
VDDQ + 0.3
0.8
Unit
V
V
V
V
V
V
Pin Capacitance (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
Limits (Min)
Limits (Max)
-7H -7L/-8H
Input Capacitance, address & control pin
CIN
2.5
3.8
5.0
Input Capacitance, CLK pin
CCLK
2.5
3.5
4.0
Data input / output capacitance
CI/O
4.0
6.5
6.5
Unit
pF
pF
pF
Document :1G5-0183
Rev.1
Page 5
5 Page 
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2.4 Operative Command Table (note 1)
HCurrent state CS RAS CAS WE Address
Command
Action
(1/3)
Notes
Idle
H X X XX
DESL
Nop or Power down
2
L H H XX
NOP or BST Nop or Power down
2
L H L H BA, CA, A10 READ/READA ILLEGAL
3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
3
L L H H BR, RA
ACT
Row active
L L H L BA, A10
PRE/PALL
Nop
L L L HX
REF/SELF
Refresh or Self refresh
4
L L L L Op-Code
MPS
Mode register access
Row active
H X X XX
DESL
Nop
L H H XX
NOP or BST Nop
L H L H BA, CA, A10 READ/READA Begin read : Determine AP
5
L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP
5
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
Precharge
6
L L L HX
REF/SELF
ILLEGAL
L L L L Op-Code
MRS
ILLEGAL
Read
H X X XX
DESL
Continue burst to end → Row active
L H H HX
NOP
Continue burst to end → Row active
L H H LX
BST Burst stop → Row active
L H L H BA, CA, A10 READ/READA Term burst, new read : Determine AP
7
L H L L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP
7,8
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
Term burst, precharging
L L L HX
REF/SELF
ILLEGAL
L L L L Op-Code
MRS
ILLEGAL
Write
H X X XX
DESL
Continue burst to end → write recovering
L H H HX
NOP
Continue burst to end → write recovering
L H H LX
BST Burst stop → Row active
L H L H BA, CA, A10 READ/READA Term burst, start read : Determine AP
7,8
L H L L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP
7
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
Term burst, precharging
9
L L L HX
REF/SELF
ILLEGAL
L L L L Op-Code
MRS
ILLEGAL
Document :1G5-0183
Rev.1
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VG36128161BT.PDF ] | |
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