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VG26V17405J-5 Schematic ( PDF Datasheet ) - Vanguard International Semiconductor

Teilenummer VG26V17405J-5
Beschreibung 4/194/304 x 4 - Bit CMOS Dynamic RAM
Hersteller Vanguard International Semiconductor
Logo Vanguard International Semiconductor Logo 




Gesamt 27 Seiten
VG26V17405J-5 Datasheet, Funktion
VIS
Description
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR
cycles are being performed. lt is packaged in JEDEC standard 26/24-pin plastic SOJ.
Features
• Single 5V( ±10%) or 3.3V(+10%,-5%) only power supply
• High speed t RAC acess time: 50/60ns
• Low power dissipation
- Active wode : 5V version 660/605 mW (Mas)
3.3V version 432/396 mW (Mas)
- Standby mode: 5V version 1.375 mW (Mas)
3.3V version 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Document:1G5-0162
Rev.1
Page 1






VG26V17405J-5 Datasheet, Funktion
VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion
(Ta = 0 to + 70 °C, VCC= + 5V ±10 ,VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
Low
power
S-version
Standby
Current
Standard
power
version
RAS-only
refresh current
EDO page mode
current
CAS-before-RAS
refresh current
Self-refresh current
(S - Version)
CAS- before- RAS long
refresh current
(S-Version)
ICC1 RAS cycling
CAS, cycling
tRC = min
TTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS Vcc -0.2V
ICC2 Dout = High-Z
TTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS Vcc -0.2V
Dout = High-Z
ICC3
RAS cycling, CAS = VIH
tRC = min
ICC4
tRC = min
ICC5
ICC8
ICC9
tRC = min
RAS, CAS cycling
tRAS 100µs
Standby: VCC- 0.2V RAS
CAS before RAS refresh:
2048 cycles / 128ms
RAS, CAS: 0V VIL 0.2V
VCC- 0.2V VIH VIH (Max)
Dout = High-Z, tRAS 300ns
VG26(V)(S)17405
Unit Notes
-5 -6
Min Max Min Max
- 120
- 110 mA 1, 2
- 2 - 2 mA
- 0.25
- 0.25 mA
2 - 2 mA
1 - 1 mA
- 120
- 110 mA 1, 2
- 90
- 120
- 80 mA 1, 3
- 110 mA 1, 2
- 350
- 500
- 350 µA
- 500 µA
Document:1G5-0162
Rev.1
Page 6

6 Page









VG26V17405J-5 pdf, datenblatt
VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Refresh Cycle
Parameter
CAS setup time (CBR refresh)
CAS hold time (CBR refresh)
RAS precharge to CAS hold time
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (CBR self refresh)
WE setup time
WE hold time
Symbol
tCSR
tCHR
tRPC
tRASS
tRPS
tCHS
tWSR
tWHR
VG26(V)(S)17405
-5 -6
Min Max Min Max Unit
5 - 5 - ns
8 - 10 - ns
5 - 5 - ns
100 - 100 - µs
90 - 110 - ns
-50 - -50 - ns
0 - 0 - ns
10 - 10 - ns
Notes
10
7
EDO Page Mode Cycle
Parameter
EDO page mode cycle time
EDO page mode CAS precharge time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
OE high hold time from CAS high
OE high pulse width
Data output hold time after CAS low
Output disable delay from WE
WE pulse width for output disable when
CAS high
Symbol
tPC
tCP
tRASP
tCPA
tCPRH
tOEHC
tOEP
tCOH
tWHZ
tWPZ
VG26(V)(S) 17405
-5 -6
Min Max Min Max Unit Notes
20 - 25 - ns
10 - 10 - ns
50 105
- 30
60 105 ns
20
- 35 ns 10, 14
30 - 35 - ns
5 - 5 - ns
10 - 10 - ns
4 - 4 - ns
3 10
3 10 ns
7 - 7 - ns
Document:1G5-0162
Rev.1
Page 12

12 Page





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