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VG26V17400EJ-5 Schematic ( PDF Datasheet ) - Vanguard International Semiconductor

Teilenummer VG26V17400EJ-5
Beschreibung 4/194/304 x 4 - Bit CMOS Dynamic RAM
Hersteller Vanguard International Semiconductor
Logo Vanguard International Semiconductor Logo 




Gesamt 25 Seiten
VG26V17400EJ-5 Datasheet, Funktion
VIS
Description
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated
with an advanced submicron CMOS technology and designed to operate from a single 5V only
or 3.3V only power supply. Low voltage operation is more suitable to be used on battery
backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported
and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin
plastic SOJ or TSOP (II).
Features
• Single 5V (±10 %) or 3.3V (±10 %) only power supply
• High speed tRAC access time : 50/60 ns
• Low power dissipation
- Active mode : 5V version 605/550 mW (Max.)
3.3V version 396/360 mW (Max.)
- Standby mode : 5V version 1.375 mW (Max.)
3.3V version 0.54 mW (Max.)
• Fast Page Mode access
• I/O level : TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)
• 4 refresh mode :
- RAS only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Self - refresh (S - version)
Document : 1G5-0142
Rev.1
Page 1






VG26V17400EJ-5 Datasheet, Funktion
VIS
DC Characteristics; 5 - Volt verion
(Ta= 0 to 70°C, VCC = + 5V±10%, Vss = 0V)
Parameter
Symbol
Test Conditions
Operating
current
Low
power
S - version
Standby Standard
Current power
version
RAS - only
refresh current
Fast page mode
current
CAS - before - RAS
refresh current
Self - refresh currant
(S - Version)
CAS - before - RAS
long refresh
current (S - Version)
RAS cycling
ICC1 CAS cycling
tRC = min.
TTL interface
RAS, CAS = VIH
Dout = high - Z
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
ICC2 TTL interface
RAS, CAS = VIH
Dout = high - Z
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
ICC3 RAS cycling, CAS = VIH
tRC = min.
ICC4
tPC = min.
ICC5 tRC = min.
RAS, CAS cycling
ICC8 tRASS 100µS
ICC9 Standby : VCC - 0.2V RAS
CAS before RAS refresh :
2048 cycles/128ms
RAS, RAS : 0V VIL 0.2V
VCC - 0.2V VIH VIH (Max)
Dout = high - Z, tRAS 300ns
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
VG26 (V) (S) 17400E
-5 -6
Unit Notes
Min Max Min Max
- 110 - 100 mA 1, 2
-2-2
mA
- 0.25
- 0.25
mA
-2-2
mA
-1-1
mA
- 110
- 80
- 110
- 350
- 500
- 100
mA
- 70
mA
- 100
mA
- 350 µA
1, 2
1,3
1, 2
- 500 µA
Document : 1G5-0142
Rev.1
Page 6

6 Page









VG26V17400EJ-5 pdf, datenblatt
VIS
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Refresh Cycle
VG26 (V) (S) 17400E
Parameter
Symbol
-5
Min Max
-6
Min Max
Unit
CAS setup time (CBR refresh)
CAS hold time (CBR refresh)
RAS precharge to CAS hold time
tCSR
tCHR
tRPC
10 - 10 - ns
10 - 10 - ns
5 - 5 - ns
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (CBR self refresh)
WE setup time
WE hold time
Fast Page Mode Cycle
tRASS
tRPS
tCHS
tWSR
tWHR
100
90
-50
0
10
- 100
- 110
- -50
-0
- 10
- µs
- ns
- ns
- ns
- ns
VG26 (V) (S) 17400E
Parameter
Symbol
-5
Min Max
-6
Min Max
Unit
Fast page mode cycle time
Fast page mode CAS Precharge time
tPC 35 - 40 - ns
tCP 10 - 10 - ns
Fast page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
Fast Page Mode Read Modify Write Cycle
tRASP
tCPA
tCPRH
50 105
- 30
30 -
60 105 ns
- 35 ns
35 - ns
VG26 (V) (S) 17400E
Parameter
Symbol
-5
Min Max
-6
Min Max
Unit
Fast page mode read - modify - write cycle CAS tCPW
45
- 55
- ns
precharge to WE delay time
Fast page mode read - modify - write cycle time tPRWC 70 - 80 - ns
Notes
10
7
Notes
20
10,14
Notes
11
Document : 1G5-0142
Rev.1
Page 12

12 Page





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