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VE28F008 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer VE28F008
Beschreibung 8 MBIT (1 MBIT x 8) FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 26 Seiten
VE28F008 Datasheet, Funktion
VE28F008
8 MBIT (1 MBIT x 8) FLASH MEMORY
Y High-Density Symmetrically Blocked
Architecture
Sixteen 64 Kbyte Blocks
Y Avionics Temperature Range
b40 C to a125 C
Y Extended Cycling Capability
10K Block Erase Cycles
160K Block Erase
Cycles per Chip
Y Automated Byte Write and Block Erase
Command User Interface
Status Register
Y System Performance Enhancements
RY BY Status Output
Erase Suspend Capability
Y Very High-Performance Read
95 ns Maximum Access Time
Y SRAM-Compatible Write Interface
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Industry Standard Packaging
40-Lead TSOP
Y ETOXTM III Nonvolatile Flash
Technology
12V Byte Write Block Erase
Y Independent Software Vendor Support
Microsoft Flash File System (FFS)
Intel’s VE28F008 8-Mbit Flash FileTM Memory revolutionizes the design of high performance and durable
mass storage memory systems for the Industrial Avionics and Military markets With its innovative features
like low power blocked architecture high read write performance and expanded temperature range any
design or mission is free from the dependence on battery backed up memory or highly sensitive and slow
rotating media drives
Using the VE28F008 in a PCMCIA 2 1 Flash Memory card ATA drive or any size or shape module will allow
data application or operating systems to be updated or collected anywhere and at anytime This data on
demand feature ensures protection from obsolesce through field or in system software updates
The VE28F008’s highly integrated Command User Interface and Write State Machine decreases the size and
complexity of system software while providing high read write and erase performance The sixteen separately
erasable 64 Kbyte blocks along with a multiple write data protection system provides assurance that highly
important data will be available when needed
The VE28F008 is offered in a 40-lead TSOP (Thin Small Outline Package) which is capable of performing in
temperatures from b40 C to a125 C It employs advanced CMOS circuitry for systems requiring low power
consumption and noise immunity The VE28F008’s 95 ns access time provides superior performance when
compared to magnetic mass storage
Manufactured on Intel’s 0 8 micron ETOXTM III process the VE28F008 provides the highest levels of quality
reliability and cost effectiveness
Microsoft is a trademark of Microsoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
May 1994
Order Number 271305-001






VE28F008 Datasheet, Funktion
VE28F008
erase and byte write circuitry Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations With the appropriate com-
mand written to the register standard microproces-
sor read timings output array data access the intelli-
gent identifier codes or output byte write and block
erase status for verification
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the VE28F008 blocks This code is copied to
and executed from system RAM during actual flash
memory update After successful completion of byte
write and or block erase code data reads from the
VE28F008 are again possible via the Read Array
command Erase suspend resume capability allows
system software to suspend block erase to read
data and execute code from any other block
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
Figure 4 Memory Map
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write freeing the system processor for other
tasks After receiving the Erase Setup and Erase
Confirm commands the state machine controls
block pre-conditioning and erase returning progress
via the Status Register and RY BY output Byte
write is similarly controlled after destination address
and expected data are supplied The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine including pulse
repetition where required and internal verification
and margining of data
Data Protection
Depending on the application the system designer
may choose to make the VPP power supply switcha-
ble (available only when memory byte writes block
erases are required) or hardwired to VPPH When
VPP e VPPL memory contents cannot be altered
The VE28F008 Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to VPP Additionally all functions are dis-
abled whenever VCC is below the write lockout volt-
age VLKO or when RP is at VIL The VE28F008 ac-
commodates either design practice and encourages
optimization of the processor-memory interface
The two-step byte write block erase Command User
Interface write sequence provides additional soft-
ware write protection
BUS OPERATION
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
Read
The VE28F008 has three read modes The memory
can be read from any of its blocks and information
can be read from the intelligent identifier or Status
Register VPP can be at either VPPL or VPPH
The first task is to write the appropriate read mode
command to the Command User Interface (array in-
telligent identifier or Status Register) The
VE28F008 automatically resets to Read Array mode
upon initial device powerup or after exit from deep
powerdown The VE28F008 has four control pins
two of which must be logically active to obtain
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VE28F008 pdf, datenblatt
VE28F008
Bus
Operation
Write
Command
Comments
Byte Write Data e 40H (10H)
Setup Address e Byte to be written
Write
Byte Write Data to be written
Address e Byte to be written
271305 – 4
FULL STATUS CHECK PROCEDURE
Standby Read
Repeat for subsequent bytes
Check RY BY
VOH e Ready VOL e Busy
or
Read Status Register
Check SR 7
1 e Ready 0 e Busy
Toggle OE or CE to update
Status Register
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Ready Array Mode
Bus
Operation
Optional
Read
Command
Comments
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Check SR 3
1 e VPP Low Detect
271305 – 5
Standby
Check SR 4
1 e Byte Write Error
SR 3 MUST be cleared if set during a byte write attempt
before further attempts are allowed by the Write State
Machine
SR 4 is only cleared by the Clear Status Register Command
in cases where multiple bytes are written before full status is
checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Figure 5 Automated Byte Write Flowchart
12

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