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V827464K24S Schematic ( PDF Datasheet ) - Mosel Vitelic Corp

Teilenummer V827464K24S
Beschreibung 2.5 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE
Hersteller Mosel Vitelic Corp
Logo Mosel Vitelic  Corp Logo 




Gesamt 14 Seiten
V827464K24S Datasheet, Funktion
MOSEL VITELIC
V827464K24S
2.5 VOLT 64M x 72 HIGH PERFORMANCE
UNBUFFERED ECC DDR SDRAM MODULE
PRELIMINARY
Features
184 Pin Unbuffered 67,108,864 x 72 bit
Organization DDR SDRAM Modules
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8196 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Component Used -6
-7 -75 -8
tCK Clock Frequency
(max.)
166 143 133 125
(PC333) (PC266A) (PC266B) (PC200)
tAC Clock Access Time
CAS Latency = 2.5
6
7 7.5 8
Description
The V827464K24S memory module is organized
67,108,864 x 72 bits in a 184 pin memory module.
The 64M x 72 memory module uses 18 Mosel-
Vitelic 32M x 8 DDR SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Module Speed
A1 PC1600 (100MHz @ CL2)
B0 PC2100B (133MHz @ CL2.5)
B1 PC2100A (133MHz @ CL2)
C0 PC2700 (166MHz @ CL2.5)
V827464K24S Rev. 1.1 September 2002
1






V827464K24S Datasheet, Funktion
MOSEL VITELIC
V827464K24S
Serial Presence Detect Information (cont.)
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 C0 A1 B0 B1 C0
28 Minimum row activate to row active delay(=tRRD)
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
15ns 15ns 15ns 12ns 3Ch 3Ch 3Ch 30h
20ns 20ns 20ns 18ns 50h 50h 50h 48h
50ns 45ns 45ns 42ns 32h 2Dh 2Dh 2Ah
256MB
40h
32 Command and address signal input setup time
1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h
33 Command and address signal input hold time
1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h
34 Data signal input setup time
0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h
35 Data signal input hold time
0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h
36-40 Superset information (may be used in future)
00h
41 SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns 65ns 65ns 60ns 46h
42 SDRAM device minimum active to autorefresh to active/auto-re- 80ns 75ns 75ns 72ns 50h
fresh time (=tRFC)
43 SDRAM device maximum device cycle time (=tCK MAX)
12ns 12ns 12ns 12ns 30h
44 SDRAM device maximum skew between DQS and DQ signals 0.6ns 0.5ns 0.5ns 0.45ns 3Ch
(=tDQSQ)
45 SDRAM device maximum read datahold skew factor (=tQHS)
1ns 0.75ns 0.75ns 0.60ns A0h
46-61 Superset information (may be used in future)
-
41h 41h
4Bh 4Bh
30h 30h
32h 32h
75h 75h
00h
3Ch
48h
30h
2Dh
60h
62 SPD data revision code
Initial release
00h
63 Checksum for Bytes 0 ~ 62
- FAh 35h 05h 5Eh
64 Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71 ....... Manufacturer JEDEC ID code
00h
72 Manufacturing location
02=Taiwan 05=China 0A=S-CH
73-90 Module part number (ASCII)
V827464K24S
91 Manufacturer revison code (For PCB)
0 00
92 Manufacturer revison code (For component)
0 00
93 Manufacturing date (Week)
--
94 Manufacturing date (Year)
--
95~98 Assembly serial #
--
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~25 Open for customer use
5
Undefined
00h
V827464K24S Rev. 1.1 September 2002
6

6 Page









V827464K24S pdf, datenblatt
MOSEL VITELIC
Package Dimensions
1.25 ± 0.006
(31.75 ±0.15)
5.25 ± 0.006
(133.350 ± 0.15)
5.077
(128.950)
V827464K24S
0.089
(2.26)
Units : Inches (Millimeters)
AB
2.55
(64.77)
1.95
(49.53)
0.26
(6.62)
0.250
(6.350)
2.175
0.071
(1.80)
Detail A
0.157
(4.00)
0.1496
(3.80)
Tolerances: + 0.005(.13) unless otherwise specified
0.039 ± 0.002
(1.000 ± 0.050)
0.0078 ±0.006
(0.20 ±0.15)
0.050
(1.270)
Detail B
0.142 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
V827464K24S Rev. 1.1 September 2002
12

12 Page





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