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V826664G24S Schematic ( PDF Datasheet ) - Mosel Vitelic Corp

Teilenummer V826664G24S
Beschreibung 512 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 64M x 64
Hersteller Mosel Vitelic Corp
Logo Mosel Vitelic  Corp Logo 




Gesamt 14 Seiten
V826664G24S Datasheet, Funktion
MOSEL VITELIC
V826664G24S
PRELIMINARY
512 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 64M x 64
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
67,108,864 x 64 bit organization.
Utilizes High Performance 32M x 8 DDR
SDRAM in SOC Packages
Single +2.5V (± 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Description
The V826664G24S memory module is organized
67,108,864 x 64 bits in a 200 pin memory module.
The 64M x 64 memory module uses 16 Mosel-
Vitelic 32M x 8 DDR SDRAM. The x64 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Component Used -6
-7 -75 -8 Units
tCK Clock Frequency 166 143 133 125 MHz
(max.)
(PC333) (PC266A) (PC266B) (PC200)
tAC Clock Access Time
CAS Latency = 2.5
6
7 7.5 8 ns
Module Speed
A1 PC1600 (100MHz @ CL2)
B0 PC2100B (133MHz @ CL2.5)
B1 PC2100A (133MHz @ CL2)
C0 PC2700 (166MHz @ CL2.5)
V826664G24S Rev. 1.0 August 2002
1






V826664G24S Datasheet, Funktion
MOSEL VITELIC
V826664G24S
Serial Presence Detect Information (cont.)
Function Supported
Byte #
Function described
A1 B0 B1 C0 A1
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
20ns
50ns
20ns 20ns
45ns 45ns
256MB
18ns
42ns
50h
32h
32 Command and address signal input setup time
1.1ns 0.9ns 0.9ns 0.75ns B0h
33 Command and address signal input hold time
1.1ns 0.9ns 0.9ns 0.75ns B0h
34 Data signal input setup time
0.6ns 0.5ns 0.5ns 0.45ns 60h
35 Data signal input hold time
0.6ns 0.5ns 0.5ns 0.45ns 60h
36-40 Superset information (may be used in future)
41 SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns 65ns 65ns 60ns 46h
42 SDRAM device minimum active to autorefresh to active/auto-refresh 80ns 75ns 75ns 72ns 50h
time (=tRFC)
43 SDRAM device maximum device cycle time (=tCK MAX)
12ns 12ns 12ns 12ns 30h
44 SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.6ns 0.5ns 0.5ns 0.45ns 3Ch
45 SDRAM device maximum read datahold skew factor (=tQHS)
1ns 0.75ns 0.75ns 0.60ns A0h
46-61 Superset information (may be used in future)
-
62 SPD data revision code
Initial release
63 Checksum for Bytes 0 ~ 62
- E8h
64 Manufacturer JEDEC ID code
Mosel Vitelic
65 -71 ....... Manufacturer JEDEC ID code
72 Manufacturing location
02=Taiwan 05=China 0A=S-CH
73-90 Module part number (ASCII)
V826664G24S
91 Manufacturer revison code (For PCB)
0
92 Manufacturer revison code (For component)
0
93 Manufacturing date (Week)
-
94 Manufacturing date (Year)
-
95~98 Assembly serial #
-
99~127 Manufacturer specific data (may be used in future)
Undefined
128~25 Open for customer use
5
Undefined
Hex value
B0 B1
50h 50h
2Dh 2Dh
40h
90h 90h
90h 90h
50h 50h
50h 50h
00h
41h 41h
4Bh 4Bh
30h 30h
32h 32h
75h 75h
00h
00h
23h F3h
40h
00h
00
00
-
-
-
00h
00h
C0
48h
2Ah
75h
75h
45h
45h
3Ch
48h
30h
2Dh
60h
4Ch
V826664G24S Rev. 1.0 August 2002
6

6 Page









V826664G24S pdf, datenblatt
MOSEL VITELIC
Package Dimensions
0.16 ± 0.039
(4.00 ± 0.10)
2.70
(67.60)
2.50
(63.60)
0.086
2.15
0.098
2.45
1 39 41
0.456
11.40
0.07
(1.8)
0.17
(4.20)
0.096
(2.40)
Z
2 40 42
1.896
(47.40)
V826664G24S
Units : Inches (Millimeters)
Full R 2x
199
2- 0.07
(1.80)
Y
200
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.04 ± 0.0039
(1.00 ± 0.1)
Detail Z
Tolerances : ±.006(.15) unless otherwise specified
0.018 ± 0.001
(0.45 ± 0.03)
0.01
(0.25)
0.024 TYP
(0.60 TYP)
Detail Y
V826664G24S Rev. 1.0 August 2002
12

12 Page





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