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V82658B04S Schematic ( PDF Datasheet ) - Mosel Vitelic Corp

Teilenummer V82658B04S
Beschreibung 64 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 8M x 64
Hersteller Mosel Vitelic Corp
Logo Mosel Vitelic  Corp Logo 




Gesamt 14 Seiten
V82658B04S Datasheet, Funktion
MOSEL VITELIC
V82658B04S
64 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 8M x 64
PRELIMINARY
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
8,388,608 x 64 bit organization.
Utilizes High Performance 8M x 16 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
4096 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Component Used -7 -75 -8 Units
tCK Clock Frequency
(max.)
143 133 125 MHz
(PC266A) (PC266B) (PC200)
tAC Clock Access Time
7
7.5
8 ns
CAS Latency = 2.5
Description
The V82658B04S memory module is organized
8,388,608 x 64 bits in a 200 pin memory module.
The 8M x 64 memory module uses 4 Mosel-Vitelic
8M x 16 DDR SDRAM. The x64 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
Module Speed
A1 PC1600 (100MHz @ CL2)
B0 PC2100B (133MHz @ CL2.5)
B1 PC2100A (133MHz @ CL2)
V82658B04S Rev. 1.2 March 2002
1






V82658B04S Datasheet, Funktion
MOSEL VITELIC
V82658B04S
Serial Presence Detect Information (cont.)
Byte #
Function described
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
32 Command and address signal input setup time
33 Command and address signal input hold time
34 Data signal input setup time
35 Data signal input hold time
36-40 Superset information (may be used in future)
41
42
43
44
45
46-61
SDRAM device minimum active to active/auto-refresh time
(=tRC)
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=tRFC)
SDRAM device maximum device cycle time (=tCK MAX)
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
SDRAM device maximum read datahold skew factor (=tQHS)
Superset information (may be used in future)
62 SPD data revision code
63 Checksum for Bytes 0 ~ 62
64 Manufacturer JEDEC ID code
65 -71 ....... Manufacturer JEDEC ID code
72 Manufacturing location
73-90 Module part number (ASCII)
91 Manufacturer revison code (For PCB)
92 Manufacturer revison code (For component)
93 Manufacturing date (Week)
94 Manufacturing date (Year)
95~98 Assembly serial #
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
Function Supported
A1 B0 B1
20ns 20ns 18ns
50ns 45ns 45ns
64MB
1.1ns 0.9ns 0.9ns
1.1ns 0.9ns 0.9ns
0.6ns 0.5ns 0.5ns
0.6ns 0.5ns 0.5ns
-
70ns 65ns 60ns
Hex value
A1 B0 B1
50h 50h 48h
32h 2Dh 2Dh
10h
B0h 90h 90h
B0h 90h 90h
60h 50h 50h
60h 50h 50h
00h
46h 41h 3Ch
80ns 75ns 67ns 50h 4Bh 43h
12ns 12ns 12ns 30h 30h 30h
0.6ns 0.5ns 0.5ns 3Ch 32h 32h
1ns 0.75ns 0.75ns A0h 75h 75h
- 00h
Initial release
00h
- BBh 01h A0h
Mosel Vitelic
40h
Mosel Vitelic
00h
01h
V82658B04S
0 00
0 00
--
--
--
Undefined
00h
Undefined
00h
V82658B04S Rev. 1.2 March 2002
6

6 Page









V82658B04S pdf, datenblatt
MOSEL VITELIC
Package Dimensions
0.16 0.039
(4.00 0.10)
2.70
(67.60)
2.50
(63.60)
0.086
2.15
0.098
2.45
1 39 41
0.456
11.40
0.07
(1.8)
0.17
(4.20)
0.096
(2.40)
Z
2 40 42
1.896
(47.40)
Y
V82658B04S
Units : Inches (Millimeters )
F ull R 2x
199
2- 0.07
(1.80)
200
0.095 Max
(2.40 Max)
0.04 0.0039
(1.00 0.10)
0.16 0.0039
(4.00 0.10)
0.04 0.0039
(1.00 0.1)
Detail Z
T olerances : .006(.15) unles s otherwis e s pecified
0.018 0.001
(0.45 0.03)
0.01
(0.25)
0.024 TYP
(0.60 TYP)
Detail Y
V82658B04S Rev. 1.2 March 2002
12

12 Page





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