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PDF V826516B04S Data sheet ( Hoja de datos )
| Número de pieza | V826516B04S | |
| Descripción | 128 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 16M x 64 | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V826516B04S
PRELIMINARY
128 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 16M x 64
Features
■ JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
16,777,216 x 64 bit organization.
■ Utilizes High Performance 8M x 16 DDR
SDRAM in TSOPII-66 Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Component Used -7 -75 -8 Units
tCK Clock Frequency
(max.)
143 133 125 MHz
(PC266A) (PC266B) (PC200)
tAC Clock Access Time
7
7.5
8 ns
CAS Latency = 2.5
Description
The V826516B04S memory module is organized
16,777,216 x 64 bits in a 200 pin memory module.
The 16M x 64 memory module uses 8 Mosel-Vitelic
8M x 16 DDR SDRAM. The x64 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
Module Speed
A1 PC1600 (100MHz @ CL2)
B0 PC2100B (133MHz @ CL2.5)
B1 PC2100A (133MHz @ CL2)
V826516B04S Rev. 1.3 March 2002
1
1 page  
MOSEL VITELIC
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
V826516B04S
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 A1 B0 B1
0 Defines # of Bytes written into serial memory at module manufacturer
128bytes
80h
1 Total # of Bytes of SPD memory device
256bytes
08h
2 Fundamental memory type
SDRAM DDR
07h
3 # of row address on this assembly
12 0Ch
4 # of column address on this assembly
9 09h
5 # of module Rows on this assembly
2 Bank
02h
6 Data width of this assembly
64 bits
40h
7 .........Data width of this assembly
- 00h
8 VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9 DDR SDRAM cycle time at CAS Latency =2.5
8ns 7.5ns 7ns 80h 75h 70h
10 DDR SDRAM Access time from clock at CL=2.5
±0.8ns ±0.75ns ±0.70ns 80h 75h 70h
11 DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00
12 Refresh rate & type
15.6us & Self refresh
80h
13 Primary DDR SDRAM width
x16 10h
14 Error checking DDR SDRAM data width
x0 00h
15 Minimum clock delay for back-to-back random column
address
tCCD=1CLK
01h
16 DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18 DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19 DDR SDRAM device attributes : CS Latency
0CLK
01h
20 DDR SDRAM device attributes : WE Latency
1CLK
02h
21 DDR SDRAM module attributes
Unbuffered
Diff Clock
20h
22 DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23 DDR SDRAM cycle time at CL =2
10ns 10ns 7.5ns A0h A0h 75h
24 DDR SDRAM Access time from clock at CL =2
±0.8ns ±0.8ns ±0.75ns 80h 80h 75h
25 DDR SDRAM cycle time at CL =1.5
---
00h
26 DDR SDRAM Access time from clock at CL =1.5
---
00h
27 Minimum row precharge time (=tRP)
28 Minimum row activate to row active delay(=tRRD)
20ns 20ns 18ns 50h 50h 48h
15ns 15ns 14ns 3Ch 3Ch 38h
V826516B04S Rev. 1.3 March 2002
5
5 Page 
MOSEL VITELIC
V826516B04S
AC Characteristics (cont.)
(PC1600)
(PC2100B) (PC2100A)
Parameter
Symbol Min Max Min Max Min Max Unit Note
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Power Down Exit Time
Exit Self Refresh to Non-Read Command
Exit Self Refresh to Read Command
Average Periodic Refresh Interval
tWPRES
tWPREH
tWPST
tMRD
tPDEX
tXSNR
tXSRD
tREFI
0
0.25
0.4
2
10
75
200
-
-
-
0.6
-
-
-
-
15.6
0
0.25
0.4
2
10
75
200
-
-
-
0.6
-
-
-
-
15.6
0
0.25
0.4
2
10
80
200
-
-
-
0.6
-
-
-
-
15.6
CLK
CLK
CLK
CLK
ns
ns
CLK
us
8
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature • Time
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Note: Operation at above absolute maximum rating can adversely affect device reliability
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
8
260 • 10
Unit
°C
°C
V
V
V
mA
W
°C • Sec
V826516B04S Rev. 1.3 March 2002
11
11 Page | ||
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| PDF Descargar | [ Datasheet V826516B04S.PDF ] | |
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