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PDF V3021 Data sheet ( Hoja de datos )
| Número de pieza | V3021 | |
| Descripción | Ultra Low Power 1-Bit 32 kHz RTC | |
| Fabricantes | ETC | |
| Logotipo |  |
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R
EM MICROELECTRONIC-MARIN SA
V3021
Ultra Low Power 1-Bit 32 kHz RTC
Features
n Supply current typically 800 nA at 3 V
n 50 ns access time with 50 pF load capacitance
n Fully operational from 2.0 V to 5.5 V
n No busy states or danger of a clock update while
accessing
n Serial communication on one line of a standard parallel
data bus or over a conventional 3 wire serial interface
n Interface compatible with both Intel and Motorola
n Seconds, minutes, hours, day of month, month, year, week
day and week number in BCD format
n Leap year and week number correction
n Time set lock mode to prevent unauthorized setting of the
current time or date
n Oscillator stability 0.3 ppm / volt
n No external capacitor needed
n Frequency measurement and test modes
n Temperature range - 40 to +85 oC
n Packages DIP8 and SO8
Typical Operating Configuration
CPU
Address
Decoder
XI
CS
RD XO
WR
V3021
I/O
Description
The V3021 is a low power CMOS real time clock. Data is
transmitted serially as 4 address bits and 8 data bits, over one
line of a standard parallel data bus. The device is accessed by
chip select (CS) with read and write control timing provided by
either RD and WR pulse (Intel CPU) or DS with advanced R/W
(Motorola CPU). Data can also be transmitted over a
conventional 3 wire serial interface having CLK, data I/O and
strobe. The V3021 has no busy states and there is no danger of
a clock update while accessing. Supply current is typically 800
nA at VDD = 3.0 V. Battery operation is supported by complete
functionality down to 2.0 V. The oscillator stability is typically 0.3
ppm/V.
Pin Assignment
DIP8 / SO8
RAM
CS
RD
WR
Applications
n Utility meters
n Battery operated and portable equipment
n Consumer electronics
n White/brown goods
n Pay phones
n Cash registers
n Personal computers
n Programmable controller systems
n Data loggers
n Automotive electronics
XI VDD
XO WR
V3021
CS RD
VSS I/O
1
Fig. 1
Fig. 2
1 page  
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Write Timing for Motorola (DS (or RD pin tied to CS) and R/W)
tCS tW
CS
DS
R/W
I/O
tADW
tDW tDH
data valid
Communication Cycles
Read Data Cycle for Intel (RD and WR Pulse)
CS
DS
WR
I/O A0 A1 A2 A3 D0 D1
D7
mP writes 4 address bits
mP reads 8 data bits
Read Data Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)
CS
DS
R/W
I/O
A0 A1 A2 A3
mP writes 4 address bits
D0 D1
D7
mP reads 8 data bits
Write Data Cycle for Intel (RD and WR Pulse)
CS
RD “ 1”
“ 0”
WR
I/O A0 A1 A2 A3
mP writes 4 address bits
D0 D1
mP reads 8 data bits
D7
5
V3021
Fig. 5c
Fig. 6a
Fig. 6b
Fig. 6c
5 Page 
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Typical Applications
V3021 Interfaced with Intel CPU (RD/WR Pulse)
8088
WR
RD
BUS A/D 0-7
BUS ADDRESS A8-A15
Decoder
D0
CS RD WR
I/O
V3021
V3021 Interfaced with Motorola CPU (Advanced R/W)
68000
R/W
LDS
BUS A/D 0-7
BUS ADDRESS A8-A15
Decoder
D0
V3021
to other peripherals
and memory
Fig. 13
to other peripherals
and memory
3 Wire Serial Interface
CS RD WR
I/O
V3021
Fig. 14
µP
CLK
DATA
Strobe
1) & 2)
CS
V3021
RD
I/O
WR
µP
Port A.0
Port A.1
Port A.2
CS
VSS
V3021
WR
RD
I/O
1) With strobe low bits are written to the V3021, and
with strobe high bits are read from the V3021
2) For serial ports with byte transfer only, an address
command cycle should be combined with every
data cycle to give 8 address bits and 8 data bits. For
example to read the current minutes, write address
data F + 3 (1111 + 0011) and then read 8 data bits.
Fig. 15
Battery Switch Over Circuit
+5V
1MW
VDD
V3021
CS I/O
Motorola BS107A or 3N171
BAT85*
BAT85*
+3 V
VSS
+5V
D0 of data bus
* Use Schottky barrier diodes. The
BAT85 has a typical VF of 250 mV at an
iF of 1 mA.
The reverse current is typically 200 nA
at a VR of 5 V. The reverse recovery time
is 5 ns. For surface mount applications
use the Philips BAT17 in SOT-23 or
other.
Fig. 16
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet V3021.PDF ] | |
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